R-Tile Avalon® Streaming FPGA IP for PCI Express* IP Core Release Notes

Download PDF
ID 683311
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core Release Notes
1. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core Release Notes x
1.1. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v12.0.0 1.2. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.6.0 1.3. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.5.0 1.4. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.4.0 1.5. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.3.0 1.6. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.2.0 1.7. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.1.0 1.8. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.0.0 1.9. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v10.0.0 1.10. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v9.0.0 1.11. R-Tile Avalon® Streaming FPGA IP for PCI Express IP core v8.0.0 1.12. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v7.0.0 1.13. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v6.0.0 1.14. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v5.0.0 1.15. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v4.0.0 1.16. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v3.0.0 1.17. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v2.0.0 1.18. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v1.0.0 1.19. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v1.0.0 1.20. R-Tile Avalon® Streaming FPGA IP for PCI Express User Guide Archives
1. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core Release Notes

1.11. R-Tile IP for PCI Express IP Core v4.0.0

Table 21.  v4.0.0 2021.12.13
Quartus® Prime Version Description Impact
21.4

Added a parameter to the IP Parameter Editor to strip the ECRC field from a TLP payload.

You can choose to remove the ECRC field from the TLP payload when the R-Tile Intel FPGA IP for PCIe is configured in TLP Bypass mode.

Enhanced the IP Parameter Editor for the Configuration Intercept Interface (CII).

You are not required to configure default values for the CII ranges in the IP Parameter Editor. You can define the CII ranges as required for your design implementation.

Table 22.  R-tile Avalon Streaming IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Configuration PCIe IP Support Timing Support
EP RP BP -1 -2 -3
16-channel PIPE Direct SCT SCT SCT 500 MHz 500 MHz N/A
Gen5 x16 1024-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x16 1024-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x16 1024-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen5 x8/x8 512-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x8/x8 512-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x8/x8 512-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen5 x4/x4/x4 256-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x4/x4/x4 256-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x4/x4/x4 256-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Level Two Title