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1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide
1.2. Design Example Detailed Description
1.3. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
1.4. Document Revision History for the JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
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1.1.2.1. Design Example Parameters
The JESD204B parameter editor includes a Example Design tab for you to specify certain parameters before generating the design example.
Parameter | Options | Description |
---|---|---|
Available Example Designs | None (Default) | No design examples selected. |
System Console Control | Design example with System Console control. | |
Example Design Files | Simulation | Generate simulation fileset. |
Synthesis | Generate synthesis fileset. | |
Generated HDL Format for Simulation | Verilog (Default) | Verilog HDL format for entire simulation fileset. |
VHDL | VHDL Platform Designer generated top-level wrapper file set. | |
Generated HDL Format for Synthesis | Verilog (Default) | Verilog HDL format for synthesis fileset. |
Example Design Customizations | Generate 3-wire SPI module | Check to enable 3-wire SPI interface instead of 4-wire SPI interface. |
Target Development Kit | None (Default) | No target development kit selected. |
Cyclone GX FPGA Development Kit | Design example targets Intel® Cyclone® 10 GX FPGA Development Kit |