Quartus® Prime Pro Edition Settings File Reference Manual
MAXIMUM_SYNCHRONIZER_LENGTH_PROTECTED
This Quartus Settings File (.qsf) assignment specifies the maximum number of registers in a row for consideration as a synchronization chain. Synchronization chains are sequences of registers with the same clock, no fan-out in between, such that the first register is fed by a pin, or by logic in another clock domain. These registers are considered for metastability analysis, and are also protected from optimizations such as retiming. When gate-level retiming is turned on, the Compiler does not move these registers. The default chain length is device-specific.
Old Name
ADV_NETLIST_OPT_METASTABLE_REGS, SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
Type
Integer
Device Support
- Agilex 3
- Intel Agilex® 5
- Intel Agilex® 7
- Arria® 10
- Cyclone® 10 GX
- Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAXIMUM_SYNCHRONIZER_LENGTH_PROTECTED <value> set_global_assignment -name MAXIMUM_SYNCHRONIZER_LENGTH_PROTECTED -entity <entity name> <value> set_instance_assignment -name MAXIMUM_SYNCHRONIZER_LENGTH_PROTECTED -to <to> -entity <entity name> <value>