Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 10/01/2025
Public
Document Table of Contents

ENABLE_DEFENSIVE_SYNTHESIS

Enable the defensive synthesis flow during compilation. Defensive synthesis looks for unsafe structures fed by registers with powerup dont-care and enables power-up care on registers which feed those structures. This protects against unexpected intial conditions from power-up if the registers are retimed.

Type

Enumeration

Values

  • Protect
  • Report
  • Waive

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Syntax

set_global_assignment -name ENABLE_DEFENSIVE_SYNTHESIS <value>
set_instance_assignment -name ENABLE_DEFENSIVE_SYNTHESIS -to <to> -entity <entity name> <value>

Default Value

Waive