Quartus® Prime Pro Edition Settings File Reference Manual
Visible to Intel only — GUID: bkl1528324508206
Ixiasoft
Visible to Intel only — GUID: bkl1528324508206
Ixiasoft
1.3.113. VERILOG_CONSTANT_LOOP_LIMIT
Defines the iteration limit for Verilog loops with loop conditions that evaluate to compile-time constants on each loop iteration. This limit exists primarily to identify potential infinite loops before they exhaust memory or trap the software in an actual infinite loop.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT <value> set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -entity <entity name> <value> set_instance_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -to <to> -entity <entity name> <value>
Default Value
5000
Example
set_global_assignment -name verilog_constant_loop_limit 3000