Mailbox Client IPs User Guide

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ID 683290
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client IPs User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client IPs User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client IP Core Interface Signals 1.5. Mailbox Client IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client IP 1.10. Accessing Quad SPI Flash Mailbox Client IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client IP User Guide Archives 1.13. Document Revision History for the Mailbox Client IP User Guide
1.4. Mailbox Client IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client IPs User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.4.1. Clock and Reset Interfaces

Table 4.  Clock and Reset Interfaces
Signal Role Width Direction Description
clk 1 Input Input clock to clock the Mailbox Client IP. The maximum frequency is 250 MHz.
reset 1 Input Reset that resets the Mailbox Client IP.

To reset the IP, assert the reset signal high for at least 2 clk cycles.

To ensure the Mailbox Client IP functions correctly when the device enters user mode, your design must include the Reset Release IP to hold the reset until the FPGA fabric entered user mode. Altera recommends using a reset synchronizer when connecting the user reset or output of the Reset Release IP to the reset port of the Mailbox Client IP. To implement the reset synchronizer, use the Reset Bridge IP available in the Platform Designer.
Note: For IP instantiation and connection guidelines in the Platform Designer, refer to the Required Communication and Host Components for the Remote System Update Design Example figure in the Stratix® 10 Configuration User Guide.
Note: For IP instantiation guidelines, refer to the respective device's Configuration User Guide.
irq 1 Output Interrupt signal. Drives the value of the AND of the interrupt status and interrupt enable registers.
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