Mailbox Client Intel® FPGA IP User Guide

Download PDF
ID 683290
Date 4/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Device Family Support 1.2. Parameters 1.3. Mailbox Client Intel FPGA Core Interface Signals 1.4. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.5. Commands and Responses 1.6. Specifying the Command and Response FIFO Depths 1.7. Enabling Cryptographic Services 1.8. Using the Mailbox Client Intel FPGA IP 1.9. Mailbox Client Intel FPGA IP Core Use Case Examples 1.10. Nios® II and Nios® V Processors HAL Driver 1.11. Mailbox Client Intel FPGA IP User Guide Archives 1.12. Document Revision History for the Mailbox Client Intel FPGA IP User Guide
1.3. Mailbox Client Intel FPGA Core Interface Signals x
1.3.1. Clock and Reset Interfaces 1.3.2. Avalon® Memory-Mapped Interface 1.3.3. AXI Manager Interface
1.4. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.4.1. Interrupt Enable Register 1.4.2. Interrupt Status Register 1.4.3. Timer Registers Incomplete Command Transaction Error SDM Backpressure Error
1.5. Commands and Responses x
1.5.1. Operation Commands 1.5.2. Error Code Responses 1.5.3. Error Code Recovery
1.10. Nios® II and Nios® V Processors HAL Driver x
1.10.1. Mailbox Client HAL API 1.10.2. LibRSU HAL API
1.10.1. Mailbox Client HAL API x
1.10.1.1. Mailbox Client Driver API
1.10.2. LibRSU HAL API x
1.10.2.1. Configuration Parameter 1.10.2.2. Error Codes 1.10.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.10.2.4. Data Type 1.10.2.5. Functions 1.10.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.4.3. Timer Registers

Use timer registers to monitor and address incomplete transactions between host and the Mailbox Client IP.

Incomplete Command Transaction Error

When a host fails to send the last command word to the Mailbox Client IP or the system stops sending data before the last word, the incomplete command transaction error occurs. Timer 1 allows you to set a specific transaction time period to complete each command. When the timer's timeout occurs, ISR[4] is set to indicate the error. To recover the system, you must reset the Mailbox Client IP.

Table 8.  Timer 1 Register
Bit Fields Access Default Value 5 Description
31 Timer 1 enable R/W 0x0 Timer 1 period enable bit. The bit is enabled once.
  • 1: Enable timer 1
  • 0: Disable timer 1

If a time out occurs, the timer 1 register becomes disabled. You must apply the Mailbox Client Intel® FPGA IP reset.

To start the timer 1, you must re-enable it again.

30:0 Timer 1 period R/W 0x7FF_FFFF

When enabled, the timer counts down the specified period as the maximum number of clock cycles the system has not received a valid command.

The timer 1 starts the count down as soon as the transaction writes the first data word into the Command FIFO (base address +0).

The timer resets when the Mailbox Client Intel® FPGA IP receives complete command transaction, indicated by successfully writing the last word into the command last word register (base address +1). When the timer 1 resets itself, it returns to its default or other defined value.

SDM Backpressure Error

SDM typically backpressures while it processes commands and sends responses. The SDM backpressure error occurs when SDM backpressures for some time period not allowing you to write any data into the Mailbox fabric and SDM. The timer 2, by setting a specific wait time, allows you detect the long wait and take steps to recover your system. When a timer's timeout occurs, ISR[5] is set to indicate an error. Note that this is a fatal error received from SDM, possibly indicating a system error. Resetting the Mailbox Client won't recover the system.
Table 9.  Timer 2 Register
Bit Fields Access Default Value 6 Description
31 Timer 2 enable R/W 0x0 Timer 2 period enable bit. The bits is enabled once.
  • 1: Enable timer 2
  • 0: Disable timer 2

If a time out occurs, the timer 2 register becomes disabled. You must apply the Mailbox Client Intel® FPGA IP reset.

To start the timer 2, you must re-enable it again.

30:0 Timer 2 period R/W 0x7FF_FFFF When enabled, the timer counts down the specified period as the maximum number of clock cycles the system has not asserted ready high signal. The SDM backpressures commands sent by host to the Mailbox Client Intel® FPGA IP.
5 Resetting the Mailbox Client IP resets the timer 1 register to the default value.
6

Resetting the Mailbox Client IP resets the timer 2 register to the default value.

Level Two Title