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1.1. Device Family Support
1.2. Parameters
1.3. Mailbox Client Intel FPGA Core Interface Signals
1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map
1.5. Commands and Responses
1.6. Specifying the Command and Response FIFO Depths
1.7. Enabling Cryptographic Services
1.8. Using the Mailbox Client Intel FPGA IP
1.9. Mailbox Client Intel FPGA IP Core Use Case Examples
1.10. Nios® II HAL Driver
1.11. Mailbox Client Intel FPGA IP User Guide Archives
1.12. Document Revision History for the Mailbox Client Intel FPGA IP User Guide
1.6. Specifying the Command and Response FIFO Depths
The optimal depth of the command and response FIFOs depends on the specific application. You should size these FIFOs to accommodate the maximum command and responses that your application requires.
The following example illustrates this point. Consider an application sends a maximum of eight back-to-back GET_TEMPERATURE commands to the FPGA core and one transceiver bank. Each command consists of a header and one command argument, specifying the mask of the temperature sensors to read. The optimal setting for the command FIFO is 16 words.
For the response FIFO, each response has one header word, and one word each for the core temperature and transceiver bank temperature. Each response is three words. The optimal setting for the response FIFO Depth is 24 words.