Intel Agilex® 7 FPGA I-Series Development Kit User Guide

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ID 683288
Date 4/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Document Revision History for the Intel Agilex® 7 FPGA I-Series Development Kit User Guide A. Development Kits Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Box Contents 1.3. Operating Conditions
2. Getting Started x
2.1. About Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. About Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch Settings 3.3. How to Generate a POF Image to Program the Flash 3.4. How to Program the Generated POF Image 3.5. The Required SmartVID QSF Assignments to Compile a Design
3.2. Default Switch Settings x
3.2.1. Default Settings 3.2.2. Perform Board Restore through Intel® Quartus® Prime Programmer
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-board Clock through Clock Controller GUI 4.4. Monitor On-board Power through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The RAM Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab
A. Development Kits Components x
A.1. Board Overview A.2. Intel Agilex® 7 FPGA I-Series A.3. PCIe* and CXL Interfaces A.4. MCIO Connector A.5. MCIO Cable Assembly Information A.6. Network Interfaces A.7. Port Controller A.8. FPGA Configuration A.9. Supported Configuration Modes A.10. Memory Interfaces A.11. I2C A.12. Clock Circuits A.13. System Power A.14. Temperature Monitoring A.15. Mechanical Requirements A.16. Board Thermal Requirements A.17. Board Operating Conditions A.18. Over Temperature Warning LED A.19. Hard Processing System
A.13. System Power x
A.13.1. Power Guidelines A.13.2. Power Distribution System A.13.3. Power Sequence A.13.4. Power Measurement
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Document Revision History for the Intel Agilex® 7 FPGA I-Series Development Kit User Guide
A. Development Kits Components
B. Additional Information

1. Overview

This user guide describes the design features and the usage of the Intel Agilex® 7 FPGA I-Series Development Kit (2x R-Tile & 1x F-Tile) board.
Table 1.   Intel Agilex® 7 FPGA I-Series Development Kit Ordering Information
Development Kit Version Ordering Code Device Part Number Serial Number
Intel Agilex® 7 FPGA I-Series Development Kit (ES2 2x R-Tile & 1x F-Tile) DK-DEV-AGI027RBES (Power Solution 2) AGIB027R29A1E2VR3 8020001
Intel Agilex® 7 FPGA I-Series Development Kit (Production 2x R-Tile & 1x F-Tile) DK-DEV-AGI027-RA (Power Solution 2) AGIB027R29A1E1VB 8030001
Intel Agilex® 7 FPGA I-Series Development Kit (ES1 2x R-Tile & 1x F-Tile) DK-DEV-AGI027R1BES (Power Solution 1) AGIB027R29A1E2VR3 8000311
Intel Agilex® 7 FPGA I-Series Development Kit (ES 2x R-Tile & 1x F-Tile) DK-DEV-AGI027RES (Power Solution 1) AGIB027R29A1E2VR0 8000001

For more details on Intel Agilex® 7 I-Series FPGAs, refer to the Intel Agilex® FPGA Portfolio page on the Intel® website.

For more information about the Intel Agilex® 7 Device Errata Sheet and User Guidelines (ES-1069) and Intel Agilex® 7 Known Issue List, contact Intel® Premier Support and quote ID #15011992053.


Section Content
Block Diagram
Box Contents
Operating Conditions

Related Information
Level Two Title

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