Agilex™ 7 FPGA I-Series Development Kit User Guide

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ID 683288
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Board 3.2. Default Settings 3.3. Performing Board Restore through Quartus® Prime Programmer 3.4. Generating a POF Image to Program the Flash 3.5. Programming the Generated POF Image 3.6. The Required SmartVID QSF Assignments to Compile a Design
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-board Power through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The RAM Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab
A. Development Kit Components x
A.1. Board Overview A.2. Agilex™ 7 FPGA I-Series A.3. PCIe* and CXL Interfaces A.4. MCIO Connector A.5. MCIO Cable Assembly Information A.6. Network Interfaces A.7. Port Controller A.8. FPGA Configuration A.9. Supported Configuration Modes A.10. Memory Interfaces A.11. I2C A.12. Clock Circuits A.13. System Power A.14. Temperature Monitoring A.15. Mechanical Requirements A.16. Board Thermal Requirements A.17. Board Operating Conditions A.18. Over Temperature Warning LED
A.13. System Power x
A.13.1. Power Guidelines A.13.2. Power Distribution System A.13.3. Power Sequence A.13.4. Power Measurement
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.11. I2C

I2C supports communication between integrated circuits on a board. It is a simple two-wire bus that consists of a serial data line (SDA) and a serial clock (SCL). The MAX® 10 and the Agilex™ 7 devices use the I2C for reading and writing to the various components on the board such as programmable clock generators, VID regulators, analog-to-digital converters (ADC), and temperature sensors.

You can use the Agilex™ 7 or MAX® 10 as the I2C host to access these devices, change clock frequencies or get status information of the board such as voltage and temperature readings.

Table 9.  I2C Device Address
Type Bus Address Device
FPGA/ MAX® 10 I2C Address I2C1 0x74 Si5391
0x6A Si52204
0x42 LTM4678/LTM4680
0x45 LTM4686
0x46 LTM4686
I2C2 0x1E FPC202
0x57/0x5F M24128
0x38 MAX31730
0x3A MAX31730
0xA0 QSFPDD_0
0xA0 QSFPDD_1
0x74 TCA9539
I2C3 0xA1 DDR4_DIMM
0xA0 DDR4_DIMM2
MAX® 10 I2C Address AVS_I2C 0x47 LTC3888
Figure 45. I2C Chain
Level Two Title