F-Tile CPRI PHY Intel® FPGA IP User Guide

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ID 683284
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. CPRI PHY Reconfiguration Interface 5.11. Datapath Avalon Memory-Mapped Interface 5.12. PMA Avalon Memory-Mapped Interface
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
1. About the F-Tile CPRI PHY Intel® FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

4.2.1. Deterministic Latency

Deterministic Latency (DL) is the ability to precisely determine the delay between the FPGA core and the PMA pins. Such delay varies from reset to reset and device to device. In most applications, the variability is acceptable to determine the actual delay within a given reset session. This section provides an example that shows the calculation delay between pins and FPGA core for the F-Tile CPRI PHY Intel® FPGA IP core.

The deterministic latency measurement methodology for Intel® Agilex™ 7 F-tile devices derives from measuring the time when a given word is present the interface to the PMA, and when that same word arrives at the FPGA core. The difference in time between these two events, when added to the PMA propagation delay, determines the total latency between the FPGA core and the serial pins. Such a calculation intrinsically includes all delays due to intermediate logic, FIFOs, and all other effects.
Table 10.  Deterministic Latency Factors
Factor Description
TxDL Transmitter delay in sampling clock cycle.

To calculate the TxDL value, read the CPRI PHY register 0xC bit[20:0]. The register provides the value in fixed point format. Bit[20:8] represents an integer, and bit[7:0] represents a fractional number.

For example:
  • Bit[20:8] = 0x27, the integer value is 39.
  • Bit[7:0] = 0xF4, the fractional value is 0.953125.
Therefore, the total delay is 39.953125 clock cycles.
Note: These values are available in simulation output.
RxDL Receiver delay in sampling clock cycle.

To calculate the RxDL value, read the CPRI PHY register 0x10 bit [20:0]. The register provides a value in fixed point format. Bit[20:8] represents an integer, and bit[7:0] represents a fractional number.

For example:
  • Bit[20:8] = 0x27, the integer value is 39.
  • Bit[7:0] = 0xF4, the fractional value is 0.953125.
Therefore, the total delay is 39.953125 clock cycles.
Note: These values are available in simulation output.
sampling_clock_period For F-Tile CPRI PHY Intel FPGA IP core:
  • Sampling clock is 250 MHz.
  • Period is 4 ns.
wa Word Aligner bit slip value (5 bit) obtained from F-tile CPRI PHY register 0x4[9:5].
eth_wa Word Aligner bit slip value (7 bit) obtained from the Datapath Avalon Memory-Mapped Interface register 0x1110[6:0].
ethlphy_wa RS-FEC Word Aligner bit slip value (lowest 5 bit) obtained from the Datapath Avalon Memory-Mapped Interface register 0x6174[4:0].
dlpulse Obtained from the Datapath Avalon Memory-Mapped Interface register (pcs_bitslip_cnt) at 0x1110 [7].
Table 11.  System Clock Frequency and Period
System Clock Frequency system_clk_div2 period
805.664062 MHz 2.482424 ns
830.078125 MHz 2.409412 ns
903.125000 MHz 2.214533 ns
Table 12.  Delay Equations for 1.2G/2.4G/3G/4.9G/6G/9.8G Variants
Delay Equations For 1.2G/2.4G/3G/4.9G/6G/9.8G Variants
Regular Simulation TX Delay (ns) TxDL * 4ns + 6 * system_clk_div2 period + 229 * UI
RX Delay (ns) RxDL * 4ns - 6 * system_clk_div2 period + (347.5 + wa) * UI
FastSim 1 TX Delay (ns) TxDL * 4ns + 6 * system_clk_div2 period + 199.5 * UI
RX Delay (ns) RxDL * 4ns - 6 * system_clk_div2 period + (339.5 + wa) * UI
Table 13.  Delay Equations for 10G/12G/24G with RS-FEC Variants
Delay Equations For 10G/12G/24G with RS-FEC Variants
Regular Simulation TX Delay (ns) TxDL * 4ns + 6 * system_clk_div2 period + 211 * UI
RX Delay (ns) RxDL * 4ns - 6 * system_clk_div2 period + (53.5 - ethlphy_wa) * UI
FastSim1 TX Delay (ns) TxDL* 4ns + 6 * system_clk_div2 period + 162.5 * UI
RX Delay (ns) RxDL * 4ns - 6 * system_clk_div2 period + (61.5 - ethlphy_wa) * UI
Table 14.  Delay Equations for 10G/12G/24G without RS-FEC Variants
Delay Equations For 10G/12G/24G without RS-FEC Variants
Regular Simulation TX Delay (ns) TxDL * 4ns + 6 * system_clk_div2 period + 211 * UI
RX Delay (ns) RxDL * 4ns - 6 * system_clk_div2 period + (53.5 - eth_wa - 33 * dlpulse) * UI
FastSim1 TX Delay (ns) TxDL * 4ns + 6 * system_clk_div2 period + 162.5 * UI
RX Delay (ns) RxDL * 4ns - 6 * system_clk_div2 period + (61.5 - eth_wa - 33 * dlpulse) * UI
Table 15.  Delay Equations for 2.4G/4.9G/9.8G/10G Tunnel Mode
Delay Equations For 10G/12G/24G without RS-FEC Variants
Regular Simulation TX Delay (ns) tx_delay * 4ns + 6 * system_clk_div2 period + 143 * UI
RX Delay (ns) rx_delay * 4ns - 6 * system_clk_div2 period + (184+wa) * UI
FastSim1 TX Delay (ns) tx_delay * 4ns + 6 * system_clk_div2 period + 96.5 * UI
RX Delay (ns) rx_delay * 4ns - 6 * system_clk_div2 period + (191.5+wa) * UI
To enable the FAST_SIM option, set the following value in your simulation script: 
set FAST_SIM_OPTIONS "+define+IP7581SERDES_UX_SIMSPEED"
To disable the FAST_SIM option, set the following value in your simulation script: 
set FAST_SIM_OPTIONS ""
1 This simulation model is not supported by the Questa* Intel® FPGA Edition simulator.
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