F-Tile CPRI PHY Intel® FPGA IP User Guide

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ID 683284
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. CPRI PHY Reconfiguration Interface 5.11. Datapath Avalon Memory-Mapped Interface 5.12. PMA Avalon Memory-Mapped Interface
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
1. About the F-Tile CPRI PHY Intel® FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

4. Functional Description

The F-Tile CPRI PHY Intel® FPGA IP core consists of the following modules:
  • F-Tile transceiver channels which consists of PMA and RS-FEC hard logic to support CPRI and Ethernet protocols. It also contains a hard PCS block that provides 64b/66b encoding scheme for 10.1376, 12.1651, and 24.33024 Gbps CPRI line rates. For more information, refer to the F-tile Architecture and PMA and FEC Direct PHY IP User Guide.
  • Soft Reset Controller—a reset controller that manages reset signals according to the F-Tile CPRI PHY Intel® FPGA IP core requirements.
  • Elastic FIFO (EFIFO)—a dual clock FIFO that matches the rate differences between the F-tile hard logic and soft logic.
  • Latency measurement—a module that generates a sync pulse to measure the datapath delay of the F-Tile CPRI PHY Intel® FPGA IP core.
  • Low Speed PCS—a soft PCS block that provides the 8b/10b encoding scheme for the CPRI line rates of 9.8 Gbps and below.
Figure 6. IP Block Diagram

Section Content
Reset Logic
Latency Measurement

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