F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 3/28/2022
Public

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Document Table of Contents

5.12. PMA Avalon Memory-Mapped Interface

Table 28.  PMA Avalon Memory-Mapped Interface Signals
Port Name Width Domain Description
i_reconfig_xcvr_addr[17:0] 18 i_reconfig_clk Address for the PMA Avalon Memory-Mapped Interface CSRs in the selected channel. Using word addressing format.
i_reconfig_xcvr_read 1 i_reconfig_clk Read command for the PMA Avalon Memory-Mapped Interface CSRs in selected the channel.
i_reconfig_xcvr_write 1 i_reconfig_clk Write command for the PMA Avalon Memory-Mapped Interface CSRs in the selected channel.
o_reconfig_xcvr_readdata[31:0] 32 i_reconfig_clk Read data from reads to the PMA Avalon Memory-Mapped Interface CSRs in the selected channel.
o_reconfig_xcvr_readdatavalid 1 i_reconfig_clk Read data from the PMA Avalon Memory-Mapped Interface CSRs is valid in the selected channel.
i_reconfig_xcvr_writedata[31:0] 32 i_reconfig_clk Data for writes to the PMA Avalon Memory-Mapped Interface CSRs in the selected channel.
o_reconfig_xcvr_waitrequest 1 i_reconfig_clk Avalon® memory-mapped interface stalling signal for operations on the PMA Avalon Memory-Mapped Interface CSRs in the selected channel.
i_reconfig_xcvr_byteenable[3:0] 4 i_reconfig_clk Byte-enable for the PMA Avalon Memory-Mapped Interface CSRs in the selected channel.