F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 3/28/2022
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 22.1
IP Version 3.2.0

The F-Tile CPRI PHY Intel® FPGA IP core provides a simulation testbench and hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

Intel® also provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

The F-Tile CPRI PHY Intel® FPGA IP core allows you to generate design examples for all supported combinations of CPRI channels and CPRI line bit rates. The testbench and design example support multiple parameter combinations of the F-Tile CPRI PHY Intel® FPGA IP core.

Figure 1. Development Steps for the Design Example
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