1.7. Arria 10 External Memory Interface IP 16.1
|Implemented fix to address hardware calibration problems with DDR4 LRDIMM interfaces. (This change is a final bit-settings change for 10AX115 devices.)
|To incorporate this fix in existing DDR4 LRDIMM designs, regenerate the DDR4 IP and recompile the design.
|Modified parameter editor for DDR4 RDIMM and LRDIMM to accept individual RDIMM/LRDIMM SPD data directly, without manual encoding. The IP then calculates the encoded RCD and DB configuration settings.
|If you are upgrading from a previous version that uses the encoded values, those values are still accepted by the new version of the IP.
|DDR3 LRDIMM usage is currently restricted. If you select LRDIMM, you will not be able to generate an external memory interface IP for DDR3.
|Cannot generate EMIF IP for DDR3 LRDIMM. Contact Intel for support.