E-Tile JESD204C Intel® FPGA IP Release Notes

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ID 683266
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. E-Tile JESD204C Intel® FPGA IP Release Notes 2. E-Tile JESD204C Intel® FPGA IP User Guide Archives 3. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives 4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
1. E-Tile JESD204C Intel® FPGA IP Release Notes x
1.1. JESD204C Intel® FPGA IP v3.1.1 1.2. JESD204C Intel® FPGA IP v2.0.0 1.3. JESD204C Intel® FPGA IP v1.1.0 1.4. JESD204C Intel® FPGA IP v1.0.0 1.5. JESD204C Intel® FPGA IP v1.0.0
1. E-Tile JESD204C Intel® FPGA IP Release Notes
2. E-Tile JESD204C Intel® FPGA IP User Guide Archives
3. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives
4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives

1. JESD204C Intel® FPGA IP Release Notes

If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the Intel® Quartus® Prime Design Suite Update Release Notes.

Intel® FPGA IP versions match the Intel® Quartus® Prime Design Suite software versions until v19.1. Starting in Intel® Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.

The Intel® FPGA IP version (X.Y.Z) number can change with each Intel® Quartus® Prime software version. A change in:

  • X indicates a major revision of the IP. If you update the Intel® Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

Section Content
JESD204C Intel FPGA IP v2.0.0
JESD204C Intel FPGA IP v1.1.0
JESD204C Intel FPGA IP v1.0.0
JESD204C Intel FPGA IP v1.0.0

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