AN 494: GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series

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ID 683261
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series
1. GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series x
1.1. GPIO Pin Expansion and I2C 1.2. I2C Interface for GPIO Pin Expansion 1.3. GPIO Pin Expansion Using I2C Bus Interface Using MAX II Devices 1.4. Acknowledgments 1.5. Document Revision History
1.2. I2C Interface for GPIO Pin Expansion x
1.2.1. I2C Interface 1.2.2. GPIO Interface
1.3. GPIO Pin Expansion Using I2C Bus Interface Using MAX II Devices x
1.3.1. Design Demonstration on the MDN-B2 Demo Board
1. GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series

1.2.1. I2C Interface

For the I2C interface, the device (I2C slave) has a built-in 7-bit address and follows the general I2C protocol. The start signal is sent by the master, followed by the 7-bit address and an R/W bit. When the address broadcast on the I2C bus matches a slave device's address, an ACK (acknowledge) signal is sent by the device followed by data according to the read or write signal sent by the master. This is then followed by another ACK signal. The exchange of data continues in this manner until the Stop (P) signal is sent by the master.

Table 1.  I2C Interface Pin Description
Signal Purpose Direction
SCL I2C Clock Output
SDA I2C Serial Data Bidirectional
Figure 2. I2C Signal Format
Level Two Title