25G Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

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ID 683252
Date 6/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. 25G Ethernet Intel® FPGA IP Quick Start Guide 2. 10G/25G Ethernet Single-Channel Design Example for Stratix® 10 Devices 3. 25G Ethernet Single-Channel Design Example for Stratix® 10 Devices 4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices 5. 25G Ethernet Intel® FPGA IP Design Example References 6. 25G Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives 7. Document Revision History for the 25G Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide
1. 25G Ethernet Intel® FPGA IP Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench x
1.3.1. Procedure
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure
1.5. Changing Target Device in Hardware Design Example x
1.5.1. Procedure
1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware x
1.6.1. Procedure
2. 10G/25G Ethernet Single-Channel Design Example for Stratix® 10 Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature 2.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
2.6. Hardware Testing x
2.6.1. Test Procedure—Design Example Without the IEEE 1588v2 Feature 2.6.2. Test Procedure—Design Example with the IEEE 1588v2 Feature
3. 25G Ethernet Single-Channel Design Example for Stratix® 10 Devices x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Compilation 3.6. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature 3.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
3.6. Hardware Testing x
3.6.1. Test Procedure—Design Example With and Without the IEEE 1588v2 Feature
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Compilation 4.6. Hardware Testing
4.3. Functional Description x
4.3.1. Design Components
4.4. Simulation x
4.4.1. Testbench 4.4.2. Simulation Design Example Components 4.4.3. Test Case
4.6. Hardware Testing x
4.6.1. Test Procedure
5. 25G Ethernet Intel® FPGA IP Design Example References x
5.1. Design Example Interface Signals 5.2. Design Example Registers 5.3. Using Transceiver Toolkit on H-Tile Production Device
1. 25G Ethernet Intel® FPGA IP Quick Start Guide
2. 10G/25G Ethernet Single-Channel Design Example for Stratix® 10 Devices
3. 25G Ethernet Single-Channel Design Example for Stratix® 10 Devices
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices
5. 25G Ethernet Intel® FPGA IP Design Example References
6. 25G Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
7. Document Revision History for the 25G Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

5.2. Design Example Registers

Table 15.  Hardware Design Example Register Map for 25G Ethernet Intel® FPGA IP Core for Stratix® 10 DevicesYou access these registers with the reg_read and reg_write functions in the System Console.

Word Offset

Register Category

Variant: Single-Channel
0X0000–0X0DFF Register range to access the Status Registers.
0X4000–0X7FFF Register range to access the Reconfiguration Registers.
0X10000–0X10001 Register range to access the Reconfiguration Registers module for 10G/25G switching.
0x1020 32-bit average_offset_fnsec_r register:
  • Read this register to obtain average offset value [47:16] in fractional nanosecond, which is derived from the offset adjustment data [96:0] of the PTP slave.
0x1021 32-bit average_offset_fnsec_to_mem register:
  • Read this register to obtain average offset value [15:0] in fractional nanosecond, which is derived from the offset adjustment data [96:0] of the PTP slave.
  • Bit [31:16]: Reserved.
0x1030 32-bit average_delay_fnsec_r register:
  • Read this register to obtain average delay value [47:16] in fractional nanosecond, which is derived from the offset adjustment data [191:96] of the PTP slave.
0x1031 32-bit average_delay_fnsec_to_mem register:
  • Read this register to obtain average delay value [15:0] in fractional nanosecond, which is derived from the offset adjustment data [191:96] of the PTP slave.
  • Bit [31:16]: Reserved.
Variant: Multi-Channel
0x00000–0x30DFF For multi-channel design examples, the base address of all channels are incremented with 0x10000. This corresponds to:
  • Channel 0 Range: 0x00300–00DFF
  • Channel 1 Range: 0x10300–10DFF
  • Channel 2 Range: 0x20300–20DFF
  • Channel 3 Range: 0x30300–30DFF
0x04000-0x37FFF For multi-channel design examples, the base address of all channels are incremented with 0x10000. This corresponds to:
  • Channel 0 Range: 0x04000-0x07FFF
  • Channel 1 Range: 0x14000-0x17FFF
  • Channel 2 Range: 0x24000-0x27FFF
  • Channel 3 Range: 0x34000-0x37FFF
Note:
  1. For Stratix® 10 H-tile production device, disable the background calibration prior to accessing the transceiver core reconfiguration register, as described in the Disabling Background Calibration section of the 25G Ethernet Intel® FPGA IP User Guide.
  2. Dynamic reconfiguration switching for 10G/25G is not available for multi-channel designs.
  3. For single-channel design example, 0x4000 is the base address of the PHY registers. For example, to read the background calibration register, type reg_read 0x4542.
  4. For multi-channel design example, the base address of the PHY registers is 0x4000 + (0x10000 * <link num>). For example, to read the background calibration register at channel 2, type reg_read 0x24542.
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