1.1.1. Timing Path and Clock Analysis
1.1.2. Clock Setup Analysis
1.1.3. Clock Hold Analysis
1.1.4. Recovery and Removal Analysis
1.1.5. Multicycle Path Analysis
1.1.6. Metastability Analysis
1.1.7. Timing Pessimism
1.1.8. Clock-As-Data Analysis
1.1.9. Multicorner Timing Analysis
1.1.10. Time Borrowing
2.1. Using Timing Constraints throughout the Design Flow
2.2. Timing Analysis Flow
2.3. Applying Timing Constraints
2.4. Timing Constraint Descriptions
2.5. Timing Report Descriptions
2.6. Scripting Timing Analysis
2.7. Using the Quartus® Prime Timing Analyzer Document Revision History
2.8. Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.4.4.5.1. Default Multicycle Analysis
2.4.4.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.4.4.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.4.4.5.4. Same Frequency Clocks with Destination Clock Offset
2.4.4.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.4.4.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.4.4.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.4.4.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.5.1. Report Fmax Summary
2.5.2. Report Timing
2.5.3. Report Timing By Source Files
2.5.4. Report Data Delay
2.5.5. Report Net Delay
2.5.6. Report Clocks and Clock Network
2.5.7. Report Clock Transfers
2.5.8. Report Metastability
2.5.9. Report CDC Viewer
2.5.10. Report Asynchronous CDC
2.5.11. Report Logic Depth
2.5.12. Report Neighbor Paths
2.5.13. Report Register Spread
2.5.14. Report Route Net of Interest
2.5.15. Report Retiming Restrictions
2.5.16. Report Register Statistics
2.5.17. Report Pipelining Information
2.5.18. Report Time Borrowing Data
2.5.19. Report Exceptions and Exceptions Reachability
2.5.20. Report Bottlenecks
2.5.21. Check Timing
2.5.22. Report SDC
2.5.23. Design Closure Summary
3.1.1. CDC Timing Overview
3.1.2. Identifying CDC Timing Issues Using Design Assistant
3.1.3. Identifying CDC Timing Issues Using Timing Reports
3.1.4. Debug CDC Example 1—Incorrect SDC Definition
3.1.5. Debug CDC Example 2—Additional Logic in the Crossing
3.1.6. Debug CDC Example 3—CDC Depending on Two Simultaneous Clock Domains
2.6.3.2. Adding and Removing Collection Items
Wildcards that you use with collection commands define collection items that the command identifies. For example, if a design contains registers with the name src0, src1, src2, and dst0, the collection command [get_registers src*] identifies registers src0, src1, and src2, but not register dst0. To identify register dst0, you must use an additional command, [get_registers dst*]. To include dst0, you can also specify a collection command [get_registers {src* dst*}].
To modify collections, use the add_to_collection and remove_from_collection commands. The add_to_collection command allows you to add additional items to an existing collection.
add_to_collection Command
add_to_collection < first collection > < second collection >
Note: The add_to_collection command creates a new collection that is the union of the two collections you specify.
The remove_from_collection command allows you to remove items from an existing collection.
remove_from_collection Command
remove_from_collection < first collection > < second collection >
The following example shows use of add_to_collection to add items to a collection.
Adding Items to a Collection
#Setting up initial collection of registers set regs1 [get_registers a*] #Setting up initial collection of keepers set kprs1 [get_keepers b*] #Creating a new set of registers of $regs1 and $kprs1 set regs_union [add_to_collection $kprs1 $regs1] #OR #Creating a new set of registers of $regs1 and b* #Note that the new collection appends only registers with name b* # not all keepers set regs_union [add_to_collection $regs1 b*]
In the Quartus® Prime software, keepers are I/O ports or registers. An .sdc file that includes get_keepers is incompatible with third-party timing analysis flows.