O-RAN Intel® FPGA IP User Guide

ID 683238
Date 11/03/2021
Public

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3.3. O-RAN Reset Transactions

The IP has five external reset ports.

The five external reset ports are:

  • rst_tx_n. Resets the O-RAN IP in the transmission direction. Resets the common header mapper, transmission window monitor and C and U-plane mapper.
  • rst_rx_n. Resets the O-RAN IP in the receiver direction. Resets the common header demapper, reception window monitor and C- and U-plane demapper.
  • rst_csr_n. Resets the O-RAN IP control and status registers. Assert to reset the IP.
  • tx_lanes_stable. Resets the O-RAN IP in the transmission direction. Deassertion indicates the transmitter clock is stable and O-RAN IP transmitter path is ready to come out from reset. Connect this reset to the Ethernet MAC output or tie to 1.
  • rx_pcs_ready. Resets the O-RAN IP in the receiver direction. Deassertion indicates the receiver clock is stable and O-RAN IP receiver path is ready to come out from reset. Connect this reset to the Ethernet MAC output or tie to 1.
Figure 15. O-RAN IP Resets

Intel expects the three external reset ports to assert together to fully reset the O-RAN IP. You can deassert the three reset ports together or deassert rst_csr_n, then reset_tx_n, and reset_rx_n to reset CSR, transmitter path, receiver path, respectively.

The reset flow occurs before the O-RAN IP starts. Deassert the Avalon Streaming application interface ready signals to indicate IP is not ready to receive any transaction.

Alternatively, you can trigger a reset after reconfiguring O-RAN IP during run time.

Figure 16. Reset DeassertionThe timing diagram shows tx_lanes_stable and rx_pcs_ready tied to 1 and both the O-RAN and Ethernet IP sharing the same CSR, transmit, and receive reset ports. On deasserting a reset,the O-RAN IP deasserts the internal IP reset and sends a request when the eCPRI IP asserts the Avalon Streaming ready signal.
Figure 17. Reset DeassertionThe timing diagram shows the tx_lanes_stable and rx_pcs_ready connected to the Ethernet MAC output interface and both the O-RAN and Ethernet IP sharing the same CSR, transmit and receive reset ports. On deasserting a reset, the Ethernet MAC cycles through the reset deassertion flow and then asserts tx_lanes_stable and rx_pcs_ready. When the O-RAN IP sees tx_lanes_stable and rx_pcs_ready assertions, the ORAN IP deasserts the internal IP reset.