O-RAN Intel® FPGA IP User Guide

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ID 683238
Date 11/03/2021
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Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP 2. Getting Started with the O-RAN Intel® FPGA IP 3. O-RAN IP Functional Description 4. O-RAN IP Registers 5. O-RAN Intel FPGA IPs User Guide Archive 6. Document Revision History for the O-RAN Intel® FPGA IP User Guide
1. About the O-RAN Intel® FPGA IP x
1.1. O-RAN Intel® FPGA IP Features 1.2. O-RAN Intel® FPGA IP Device Family Support 1.3. Release Information for the O-RAN Intel® FPGA IP 1.4. O-RAN Intel® FPGA IP Performance and Resource Utilization
2. Getting Started with the O-RAN Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the O-RAN IP 2.2. Parameterizing the O-RAN IP 2.3. Generated IP File Structure
2.2. Parameterizing the O-RAN IP x
2.2.1. O-RAN IP Parameters
3. O-RAN IP Functional Description x
3.1. O-RAN IP Signals 3.2. O-RAN Intel® FPGA IP Error Handling 3.3. O-RAN Reset Transactions 3.4. O-RAN IP Streaming Mode 3.5. O-RAN IP Performance Counters 3.6. O-RAN IP Transmission and Reception Window Threshold
1. About the O-RAN Intel® FPGA IP
2. Getting Started with the O-RAN Intel® FPGA IP
3. O-RAN IP Functional Description
4. O-RAN IP Registers
5. O-RAN Intel FPGA IPs User Guide Archive
6. Document Revision History for the O-RAN Intel® FPGA IP User Guide

3.6. O-RAN IP Transmission and Reception Window Threshold

The topic refers to Figure 2-10 : Timing relations per symbol IQ in DL direction (U-Plane and C-Plane) and Figure 2-11 : Timing relations per symbol IQ in UL direction (U-Plane and C-Plane) in the O-RAN Fronthaul Working Group Control, User and Synchronization Plane Specification.

Downlink User Plane

For U-plane DL data flow (use symbol #0 transmission as an example):

  • At t = 0: time of transmission (at air interface) of the first sample for symbol #0 (see tDL = 0)
  • At t = - T2a_min_up: O-RU has a fixed data processing delay (T2a_min_up). To meet air interface time for symbol#0 transmission at t = 0, symbol#0, present data on time for the processing unit (yellow block).

For symbol#0, start of processing time t = 0 – T2a_min_up = - T2a_min_up

End of reception window is the latest time that O-RU can accept U-plane DL data for a specific symbol before start of data processing. If U-plane DL data arrives earlier than this time and is within reception window range, DL data may wait inside reception window buffer until the start of processing time. Hence the end of reception window is the same time point as the start of processing time.

For symbol#0, end of reception window time t = 0 – T2a_min_up = - T2a_min_up.

Start of reception window is this earliest time that O-RU can accept U-plane DL data for a specific symbol prior to start of data processing. If U-plane DL data arrives later than this time and is within reception window range, DL data waits inside reception window buffer.

For symbol#0, start of reception window time t = 0 - T2a_max_up = - T2a_max_up

O-RU reception window range = T2a_max_up – T2a_min_up

The fixed data processing delay in O-RU depends on your O-RU design not the O-RAN IP. You must program the O-RU processing delay from O-RAN IP to antenna into t2a_min up register.

You determine the reception window duration through the number OFDM symbols that can be buffer within O-RU. The O-RAN IP doesn’t provide any buffering of the OFDM symbols and it depends on your O-RU design.

Assuming the processing delay between O-RAN IP to antenna is 200 µs and O_RU is capable of buffering maximum of 3 OFDM symbols, program the following vlaues into the t2a_min_up and t2a_max_up registers:

  • t2a_min_up register (in ns) = 200 µs = 0x0003_0D40
  • t2a_max_up register (in ns) = 3 OFDM symbols (210 µs) = 0x0003_3450

Allocating three OFDM symbols, T2a_max_up = 210 + 200 = 410 us = 0X0006_4190.

Downlink Control Plane

For C-plane to support DL data flow (use symbol #n = 0 transmission as an example), focus on the green path and apply the same principles to relate the reception window.

Using the same example as the downlink user plane:

  • t2a_min_cp_dl register (in ns) = 200µs = 0x0003_0D40
  • t2a_max_cp_dl register (in ns) = 3 OFDM symbols (210 µs) = 0x0003_3450

Allocating three OFDM symbols, T2a_max_up = 210 + 200 = 410 us = 0X0006_4190.

Uplink User Plane

For U-plane UL data flow (use symbol #n = 0 reception as an example):

At t = 0 : time of reception (at air interface) of the first sample for symbol #0 (see tUL = 0)

At t = 0 + Ta3_min_up : O-RU has a fixed data processing delay (Ta3_min_up). Air interface data is immediately presented to data processing unit (yellow block).

For symbol#0, end of processing = 0 + Ta3_min_up = Ta3_min_up

Start of transmission window is the earliest time that O-RU can send U-plane UL for a specific symbol out to transport interface. The earliest time is immediately after data processing.

For symbol#0, start of transmission window = 0 + Ta3_min_up = Ta3_min_up.

End of transmission window is the latest time that O-RU can send U-plane UL data for a specific symbol out to transport interface.

For symbol#0, end of transmission window = 0 + Ta3_max_up = Ta3_max_up.

O-RU transmission window range = Ta3_max_up – Ta3_min_up

The fixed data processing delay in O-RU is dependent on your O-RU design not the O-RAN IP. You must program the O-RU processing delay from the antenna to the O-RAN IP into the ta3_min_up register.

You determine the transmission window duration through the latest time that O-RU can send UL data for a specific symbol and depends on user O-RU design.

Assuming processing delay between antenna to O-RAN IP is 100 µs and latest time O_RU can send UL data for a specific symbol is 150 µs, program the following values into the ta3_min_up and ta3_max_up registers:

  • ta3_min_up register (in ns) = 100µs = 0x0001_86A0
  • ta3_max_up register (in ns) = 150 µs = 0x0002_49F0

Uplink Control Plane

For C-plane to support UL data flow (use symbol #n = 0 transmission as an example), focus on the green path and apply the same principles to relate the reception window.

Using the same example as the uplink user plane:

  • ta3_min_cp_ul register (in ns) = 200 µs = 0x0003_0D40
  • ta3_max_cp_ul register (in ns) = 3 OFDM symbols (210 µs) = 0x0003_3450
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