1.2. Using MAX II Devices as Level Shifters
The detailed description of the implementation is based on the MAX II devices. This application can also be implemented in MAX V and MAX 10 devices.
MAX II devices are designed to tolerate all types of power-on sequences making them ideal for multiple voltage systems where it is critical to maintain a particular power-on sequence.
You can configure each I/O bank to operate at a particular voltage using its VCCIO pin. A single device can support 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces and each individual bank can support a different standard. In addition, each I/O bank can support multiple standards with the same VCCIO for input and output pins. The number of I/O banks for a particular device depends on its part number.
Figure 1. Implementing a Multi-Voltage System by Voltage Level Shifting
The I/O buffer of the MAX II devices is programmable and supports a wide range of I/O voltage standards. Each I/O bank can be programmed to comply with a different I/O standard, such as the following:
- 3.3-V LVTTL/LVCMOS
- 2.5-V LVTTL/LVCMOS
- 1.8-V LVTTL/LVCMOS
- 1.5-V LVCMOS
In addition to these standards that are supported by all MAX II devices (on the EPM1270 and EPM2210 devices) I/O Bank 3 also includes a 3.3-V PCI I/O standard interface capability. MAX II devices with MultiVolt core I/O operation capability allow the core and I/O blocks of the device to be powered up with separate supply voltages. The VCCINT pins supply power to the device core and the VCCIO pins supply power to the device I/O buffers. Therefore, the MAX II devices can receive inputs from, or drive outputs to devices with different voltage levels by shifting from one value on one I/O bank to a different value on another I/O bank.
You can implement this design with an EPM240 device or any other MAX II devices, all of which have more than one I/O bank. Eight inputs are powered at 2.5V and eight outputs are powered at 1.8V to achieve 2.8V to 1.8V level translation. This design example is implemented in three basic steps that involve determining the physical pins (pin assignments), setting pin attributes in the Quartus® II software and relevant buffers assignment, and signal paths between input pins and output pins (this is accomplished by the source code).
Figure 2. Voltage Level Shifter Demonstration Circuit for MAX II Devices with Two I/O Banks
| Signal | Pin | Signal | Pin |
|---|---|---|---|
| input_bus[7] | Pin 38 | input_bus[6] | Pin 37 |
| input_bus[5] | Pin 36 | input_bus[4] | Pin 35 |
| input_bus[3] | Pin 34 | input_bus[2] | Pin 33 |
| input_bus[1] | Pin 30 | input_bus[0] | Pin 29 |
| output_bus[7] | Pin 100 | output_bus[6] | Pin 99 |
| output_bus[5] | Pin 98 | output_bus[4] | Pin 97 |
| output_bus[3] | Pin 96 | output_bus[2] | Pin 95 |
| output_bus[1] | Pin 92 | output_bus[0] | Pin 91 |
Assign the I/O pins in the Pin Planner as the following:
- Input pins bank 1 are assigned a 2.5-V I/O standard.
- Output pins on bank 2 are assigned a 1.8-V I/O standard.