O-RAN Intel® FPGA IP Design Example User Guide

ID 683218
Date 2/20/2023

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5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.02.20 22.1 1.7.0 Added Xcelium steps to Simulating the O-RAN IP Design Example for Intel Agilex F-Tile Devices
2022.06.20 22.1 1.7.0
  • Added support for Intel Agilex I-series Transceiver SoC Development Kit
  • Added Questa simulator instructions
  • Removed --use-quartus-top-names from Simulating the Design Example.
2021.09.14 21.2 1.5.1
  • Added new Number of channels parameter.
  • Added new System Console Printout figures.
  • Changed block diagram
  • Changed clk_ref description
  • Replaced Test generator and verifier Avalon memory-mapped register table
2021.06.30 21.1 1.4.0 Added support for Intel Agilex 10 devices.
2020.11.30 20.3 1.1.0 Initial release.

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