SDI II Intel® Arria 10 FPGA IP Design Example User Guide

ID 683209
Date 10/08/2021
Public

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2.7. Hardware Setup

To run the hardware test for parallel loopback designs, connect an SDI video generator to the receiver input pin.

  • Connect an external video analyzer to the TX instance to verify full functionality.
  • To validate if the RX core locks to the signal and receives the video data correctly, use the on-board LEDs that display the RX status.

To run the hardware test for serial loopback designs, connect the transmitter output pin directly to the receiver input pin.

  • To validate if the RX core locks to the signal and receives the video data correctly, use the on-board LEDs that display the RX status.
  • You may also connect an SDI signal analyzer to the transmitter output pin to view the generated image.
Figure 16.  Intel® Arria® 10 Development Board User LEDs
Table 17.  On-board User LED Functions
LEDs Function
D3–D5 Indicates the receiver video standard:
  • 000: SD-SDI
  • 001: HD-SDI
  • 010: 3G Level B 10-bit Multiplex
  • 011: 3G Level A 10-bit Multiplex
  • 100: 6G 10-bit Multiplex Type 2
  • 101: 6G 10-bit Multiplex Type 1
  • 110: 12G 10-bit Multiplex Type 2
  • 111: 12G 10-bit Multiplex Type 1
D6 Shows the slower version of the TX transceiver parallel clock
D7 Shows the slower version of the RX transceiver parallel clock
D8 Illuminates when align_locked asserts
D9 Illuminates when trs_locked asserts
D10 Illuminates when frame_locked asserts

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