FIR II IP Intel® FPGA IP: User Guide

ID 683208
Date 9/17/2024
Public
Document Table of Contents

4.4.2. Channelization

The number of wires and the number of channels carried on each wire are determined by parameterization, which you can specify using the following variables:
  • clockRate is the system clock frequency (MHz).
  • inputRate is the data sample rate per channel (MSPS).
  • inputChannelNum is the number of channels. Channels are enumerated from 0 to inputChannelNum–1.
  • The period (or TDM factor) is the ratio of the clock rate to the sample rate and determines the number of available time slots.
  • ChanWireCount is the number of channel wires required to carry all the channels. It can be calculated by dividing the number of channels by the TDM factor. More specifically:
    • PhysChanIn = Number of channel input wires
    • PhysChanOut = Number of channel output wires
  • ChanCycleCount is the number of channels carried per wire. It is calculated by dividing the number of channels by the number of channels per wire. The channel signal counts from 0 to ChanCycleCount–1. More specifically:
    • ChansPerPhyIn = Number of channels per input wire
    • ChansPerPhyOut = Number of channels per output wire

If the number of channels is greater than the clock period, multiple wires are required. Each FIR II IP core in your design is internally vectorized to build multiple FIR filters in parallel.

Figure 14. Channelization of Two Channels with a TDM Factor of 3 A TDM factor of 3 combines two input channels into a single output wire. (inputChannelNum = 2, ChanWireCount = 1, ChanCycleCount = 2). This example has three available time slots in the output channel and every third time slot has a ‘don't care’ value when the valid signal is low. The value of the channel signal while the valid signal is low does not matter.
Figure 15. Channelization for Four Channels with a TDM Factor of 3 A TDM factor of 3 combines four input channels into two wires (inputChannelNum = 4, ChanWireCount = 2, ChanCycleCount = 2). This example shows two wires to carry the four channels and the cycle count is two on each wire. The channels are evenly distributed on each wire leaving the third time slot as don't care on each wire.

The channel signal is used for synchronization and scheduling of data. It specifies the channel data separation per wire. Note that the channel signal counts from 0 to ChanCycleCount–1 in synchronization with the data. Thus, for ChanCycleCount = 1, the channel signal is the same as the channel count, enumerated from 0 to inputChannelNum–1.

For a case with single wire, the channel signal is the same as a channel count.

Figure 16. Four Channels on One Wire with No Invalid Cycles

For ChanWireCount > 1, the channel signal specifies the channel data separation per wire, rather than the actual channel number. The channel signal counts from 0 to ChanCycleCount–1 rather than 0 to inputChannelNum–1.

Figure 17. Four Channels on Two Wires with No Invalid Cycles

Notice that the channel signal remains a single wire, not a wire for each data wire. It counts from 0 to ChanCycleCount–1.

Figure 18. Four Channels on Four Wires