High-Definition Multimedia Interface (HDMI) Intel® FPGA IP Release Notes

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ID 683199
Date 4/09/2024
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1. HDMI Intel® FPGA IP Release Notes
1. HDMI Intel® FPGA IP Release Notes x
1.1. HDMI Intel® FPGA IP v19.7.4 1.2. HDMI Intel® FPGA IP v19.7.3 1.3. HDMI Intel® FPGA IP v19.7.2 1.4. HDMI Intel® FPGA IP v19.7.0 1.5. HDMI Intel® FPGA IP v19.6.1 1.6. HDMI Intel® FPGA IP v19.6.0 1.7. HDMI Intel® FPGA IP v19.5.0 1.8. HDMI Intel® FPGA IP v19.4.0 1.9. HDMI Intel® FPGA IP v19.3.0 1.10. HDMI Intel® FPGA IP v19.1 1.11. HDMI Intel® FPGA IP v18.1 Update 1 1.12. HDMI Intel® FPGA IP v18.1 1.13. HDMI Intel® FPGA IP v18.0 1.14. Intel FPGA HDMI IP Core v17.1 1.15. HDMI IP Core v17.0 1.16. HDMI IP Core v16.1 1.17. HDMI IP Core v16.0 1.18. HDMI IP Core v15.1 1.19. HDMI IP Core v15.0 Update 1 1.20. HDMI IP Core v15.0 1.21. HDMI IP Core v14.1 1.22. HDMI Intel® FPGA IP User Guide Archives 1.23. HDMI Arria® 10 FPGA IP Design Example User Guide Archives 1.24. HDMI Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.25. HDMI Stratix® 10 FPGA IP Design Example User Guide Archives
1. HDMI Intel® FPGA IP Release Notes

1.4. HDMI Intel® FPGA IP v19.7.0

Table 6.  19.7.0 2022.07.01
Quartus® Prime Version Description Impact
22.2 Added AXI4-Stream (full variant) interface support to the “Agilex HDMI RX-TX Retransmit” design example:
  • To use AXI interface, select AXIS-VVP Full for the Enable Active Video Protocol option in the IP tab.
  • Turn on or off the Video in and out use the same clock option in the Advanced Configuration tab to generate the AXI design example with the following settings:
    • Turn on—generates a design example without video frame buffer
    • Turn off—generates a design example with video frame buffer
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Table 7.  19.7.0 2022.04.04
Quartus® Prime Version Description Impact
22.1
  • Enabled multi-rate support for HDMI Agilex™ 7 Design Example.
  • Enabled Video Stream over AXI interface (AXI Bridge).
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