High-Definition Multimedia Interface (HDMI) Intel® FPGA IP Release Notes

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ID 683199
Date 4/09/2024
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1. HDMI Intel® FPGA IP Release Notes
1. HDMI Intel® FPGA IP Release Notes x
1.1. HDMI Intel® FPGA IP v19.7.4 1.2. HDMI Intel® FPGA IP v19.7.3 1.3. HDMI Intel® FPGA IP v19.7.2 1.4. HDMI Intel® FPGA IP v19.7.0 1.5. HDMI Intel® FPGA IP v19.6.1 1.6. HDMI Intel® FPGA IP v19.6.0 1.7. HDMI Intel® FPGA IP v19.5.0 1.8. HDMI Intel® FPGA IP v19.4.0 1.9. HDMI Intel® FPGA IP v19.3.0 1.10. HDMI Intel® FPGA IP v19.1 1.11. HDMI Intel® FPGA IP v18.1 Update 1 1.12. HDMI Intel® FPGA IP v18.1 1.13. HDMI Intel® FPGA IP v18.0 1.14. Intel FPGA HDMI IP Core v17.1 1.15. HDMI IP Core v17.0 1.16. HDMI IP Core v16.1 1.17. HDMI IP Core v16.0 1.18. HDMI IP Core v15.1 1.19. HDMI IP Core v15.0 Update 1 1.20. HDMI IP Core v15.0 1.21. HDMI IP Core v14.1 1.22. HDMI Intel® FPGA IP User Guide Archives 1.23. HDMI Arria® 10 FPGA IP Design Example User Guide Archives 1.24. HDMI Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.25. HDMI Stratix® 10 FPGA IP Design Example User Guide Archives
1. HDMI Intel® FPGA IP Release Notes

1.7. HDMI Intel® FPGA IP v19.5.0

Table 13.  v19.5.0 2020.09.28
Quartus® Prime Version Description Impact
20.3

The HDMI Intel® FPGA IP is repackaged.

Added the following new parameters to include a RAM for storing EDID and I2C master or slave depending on the selected direction.
  • Include I2C
  • Include EDID RAM
  • EDID RAM size
  • RAM file path
  • HPD polarity
 These changes are optional. If you do not upgrade your IP core, it does not have these new features.

Made changes in the interface as a result of the repackaging. Refer to the Source Interfaces and Sink Interfaces section in the HDMI Intel FPGA IP User Guide for more information.

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