DisplayPort Intel FPGA IP Release Notes

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ID 683194
Date 4/18/2023
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Release Notes
1. DisplayPort Intel® FPGA IP Release Notes x
1.1. DisplayPort Intel® FPGA IP v20.0.1 1.2. DisplayPort Intel® FPGA IP v20.0.0 1.3. DisplayPort Intel® FPGA IP v19.4.0 1.4. DisplayPort Intel® FPGA IP v19.3.0 1.5. DisplayPort Intel® FPGA IP v19.1 1.6. DisplayPort Intel® FPGA IP v18.1 Update 1 1.7. DisplayPort Intel® FPGA IP v18.1 1.8. DisplayPort Intel® FPGA IP v18.0 1.9. Intel FPGA DisplayPort IP Core v17.1 1.10. DisplayPort IP Core v17.0 1.11. DisplayPort IP Core v16.1 1.12. DisplayPort IP Core v16.0 1.13. DisplayPort IP Core v15.1 1.14. DisplayPort IP Core v15.0 1.15. DisplayPort IP Core v14.1 1.16. DisplayPort Intel® FPGA IP User Guide Archives 1.17. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives 1.18. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.19. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
1. DisplayPort Intel® FPGA IP Release Notes

1.1. DisplayPort Intel® FPGA IP v20.0.1

Table 1.  v20.0.1 2023.04.18
Intel® Quartus® Prime Version Description Impact
23.1
  • Enabled support for DisplayPort Intel Agilex 7 F-tile B0 Design Example.
  • Enabled HDCP over DisplayPort 1.4 on Intel Agilex 7 F-tile Design Example.
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Table 2.  v20.0.1 2022.09.26
Intel® Quartus® Prime Version Description Impact
22.3
  • Added support for DisplayPort 2.0 UHBR10 data rate for Intel® Agilex™ (F-Tile) design examples.
  • Updated the IP Resource Utilization table.
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Table 3.  v20.0.1 2022.06.21
Intel® Quartus® Prime Version Description Impact
22.2
  • Enabled UHBR135 and UHBR20 MAX_LINK_RATE for Intel® Stratix® 10 H-tile devices only.
  • Enabled two new DisplayPort Design Example Variants for Intel® Agilex™ F-tile devices:
    • SST Parallel Loopback without PCR
    • SST Parallel Loopback with AXIS Video Interface
  • Enabled new DisplayPort Design Example Variants: TX-only and RX-only for Intel® Cyclone® 10 devices. Refer to DisplayPort Intel Cyclone 10 FPGA IP Design Example User Guide for more information.
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Table 4.  v20.0.1 2022.04.04
Intel® Quartus® Prime Version Description Impact
22.1
  • Enabled new DisplayPort Design Example Variants: TX-only and RX-only for Intel® Stratix® 10 H-tile and L-tile devices.
  • Enabled Video Stream over AXI interface (AXI Bridge).
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