Visible to Intel only — GUID: ovw1549516060578
Ixiasoft
1.1. DisplayPort Intel® FPGA IP v20.0.1
1.2. DisplayPort Intel® FPGA IP v20.0.0
1.3. DisplayPort Intel® FPGA IP v19.4.0
1.4. DisplayPort Intel® FPGA IP v19.3.0
1.5. DisplayPort Intel® FPGA IP v19.1
1.6. DisplayPort Intel® FPGA IP v18.1 Update 1
1.7. DisplayPort Intel® FPGA IP v18.1
1.8. DisplayPort Intel® FPGA IP v18.0
1.9. Intel FPGA DisplayPort IP Core v17.1
1.10. DisplayPort IP Core v17.0
1.11. DisplayPort IP Core v16.1
1.12. DisplayPort IP Core v16.0
1.13. DisplayPort IP Core v15.1
1.14. DisplayPort IP Core v15.0
1.15. DisplayPort IP Core v14.1
1.16. DisplayPort Intel® FPGA IP User Guide Archives
1.17. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives
1.18. DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide Archives
1.19. DisplayPort Stratix® 10 FPGA IP Design Example User Guide Archives
Visible to Intel only — GUID: ovw1549516060578
Ixiasoft
1.6. DisplayPort Intel® FPGA IP v18.1 Update 1
18.1.1 December 2018
- For Stratix® 10 devices, enabled Pixel Clock Recovery function.
- Changed Synopsys Design Constraints to entity-based Synopsys Design Constraints.
- Cleaned up compilation warnings found in Stratix® 10 design example with pixel clock recovery.
- Enabled Stratix® 10 design example with Pixel Clock Recovery variant.
- Enabled initiation of Tx in software regardless of the setting of DP_SUPPORT_EDID_PASSTHRU.
- Fixed an Arria® 10 design example when no display output occurred in non GPU mode.
- Enabled extended receiver capabilities when the maximum link rate is HBR3.
- For Stratix® 10 H-tile devices, added VID_OPERATION_MODE "PMBUS MASTER" and PWRMGMT settings to the video connectivity design example IP .qsf file to enable Stratix® 10 SmartVID and power management capabilities.
Related Information