IOPLL Intel FPGA IP v18.0
|Renamed Intel FPGA IOPLL IP core to IOPLL Intel FPGA IP core as per Intel rebranding.||—|
|Added new settings to reduce jitter peaking: charge pump current, loop resistance, and ripplecap settings.||—|
|Added a new GUI parameter: Create a permit_cal signal to connect with an upstream PLL to export the permit_cal input.||—|
|Added a new input signal: permit_cal. Connecting this permit_cal port to the locked output port of the upstream I/O PLL ensures that the cascaded I/O PLLs are calibrated in the correct order.||—|
|Improved compensation accuracy.||—|
|Decreased IP simulation time.||—|
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