HDMI Arria® 10 FPGA IP Design Example User Guide

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ID 683156
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Arria® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example (Support FRL = 0) 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Arria® 10 FPGA IP Design Example User Guide Archives 6. Revision History for HDMI Arria® 10 FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Arria® 10 Devices x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Compiling and Testing the Design 1.4. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features 2.16. Upgrading Your Design
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.15. Debugging Features x
2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement
3. HDMI 2.0 Design Example (Support FRL = 0) x
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram 3.2. Hardware and Software Requirements 3.3. Directory Structure 3.4. Design Components 3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.6. Clocking Scheme 3.7. Interface Signals 3.8. Design RTL Parameters 3.9. Hardware Setup 3.10. Simulation Testbench 3.11. Upgrading Your Design
4. HDCP Over HDMI 2.0/2.1 Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios® V Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines
4.1. High-bandwidth Digital Content Protection (HDCP) x
4.1.1. HDCP Over HDMI Design Example Architecture
4.3. Design Walkthrough x
4.3.1. Setting Up the Hardware 4.3.2. Generating the Design 4.3.3. Including HDCP Production Keys 4.3.4. Compiling the Design 4.3.5. Viewing the Results
4.3.3. Including HDCP Production Keys x
4.3.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
4.3.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file
4.3.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer
4.3.5. Viewing the Results x
4.3.5.1. Push Buttons and LED Functions
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Arria® 10 FPGA IP Design Example User Guide

2.8. Running the Design in Different FRL Rates

You may run your design in different FRL rates, other than the external sink's default FRL rate.

To run the design in different FRL rates:

  1. Toggle the on-board user_dipsw0 switch to ON position.
  2. Open the Nios® V command shell, then type juart-terminal.
  3. Key in the following commands and press Enter to execute.
Command Description
h Show the help menu.
r0 Update the RX maximum FRL capability to FRL rate 0 (TMDS only).
r1 Update the RX maximum FRL capability to FRL rate 1 (3 Gbps).
r2 Update the RX maximum FRL capability to FRL rate 2 (6 Gbps, 3 lanes).
r3 Update the RX maximum FRL capability to FRL rate 3 (6 Gbps, 4 lanes).
r4 Update the RX maximum FRL capability to FRL rate 4 (8 Gbps).
r5 Update the RX maximum FRL capability to FRL rate 5 (10 Gbps).
r6 Update the RX maximum FRL capability to FRL rate 6 (12 Gbps).
t1 TX configures link rate to FRL rate 1 (3 Gbps).
t2 TX configures link rate to FRL rate 2 (6 Gbps, 3 lanes).
t3 TX configures link rate to FRL rate 3 (6 Gbps, 4 lanes).
t4 TX configures link rate to FRL rate 4 (8 Gbps).
t5 TX configures link rate to FRL rate 5 (10 Gbps).
t6 TX configures link rate to FRL rate 6 (12 Gbps).
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