2. Best Practices for Coding and Compiling Your Component
- Understand FPGA Concepts
A key best practice to help you get the most out of the Intel® HLS Compiler is to understand important concepts about FPGAs. With an understanding of FPGA architecture, and some FPGA hardware design concepts and methods, you can create better designs that take advantage your target FPGA devices.
- Interface Best Practices
With the Intel® High Level Synthesis Compiler, your component can have a variety of interfaces: from basic wires to the Avalon Streaming and Avalon Memory-Mapped Host interfaces. Review the interface best practices to help you choose and configure the right interface for your component.
- Loop Best Practices
The Intel® High Level Synthesis Compiler pipelines your loops to enhance throughput. Review these loop best practices to learn techniques to optimize your loops to boost the performance of your component.
- Memory Architecture Best Practices
The Intel® High Level Synthesis Compiler infers efficient memory architectures (like memory width, number of banks and ports) in a component by adapting the architecture to the memory access patterns of your component. Review the memory architecture best practices to learn how you can get the best memory architecture for your component from the compiler.
- System of Tasks Best Practices
Using a system of HLS tasks in your component enables a variety of design structures that you can implement including executing multiple loops in parallel and sharing an expensive compute block.
- Datatype Best Practices
The datatypes in your component and possible conversions or casting that they might undergo can significantly affect the performance and FPGA area usage of your component. Review the datatype best practices for tips and guidance how best to control datatype sizes and conversions in your component.
- Alternative Algorithms
The Intel® High Level Synthesis Compiler lets you compile a component quickly to get initial insights into the performance and area utilization of your component. Take advantage of this speed to try larger algorithm changes to see how those changes affect your component performance.