F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/11/2023
Public

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7.1. FASTSIM Mode Support

In the FASTSIM mode, simplified PMA abstract model is used to improve the overall simulation time for F-Tile Avalon-ST IP for PCI Express. The PMA model has a compile time switch “IP7581SERDES_UX_SIMSPEED” to use a simplified PMA abstract model. If this switch is not defined by compile environment, then a detailed or existing model is used.

The following error and warning messages are expected in FASTSIM mode as the PHY calibration is bypassed and are safe to be waived when simulated with Synopsys* Verification:
  • UVM_ERROR /p/psg/EIP/synopsys/vip/vg_P-2019.06F/vip/svt/pcie_test_suite_svt/P-2019.06-1/design_dir/src/sverilog/vcs/pciesvc_serdes.sv(242) @ 124192.730 ns: 
    uvm_test_top.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail: ACTIVE_PL_LANE_SERDES:PROTOCOL:serdes_clk_slowdown_0] : 
    New larger bit seen, but not at least 2x old bit - clock has likely slowed down (was 0.400000, now is 0.680000 ns) - SERDES unlocked. 
    CLK_TOLERANCE is set to 0.028000 and ALLOW_RECOVERED_CLK_WIDTH_ADJUSTMENTS is set to 1. 
    If the bit stream is capable of being 'locked' to then set CLK_TOLERANCE to value 0.010000(10,000ppm).
  • UVM_ERROR /p/psg/EIP/synopsys/vip/vg_P-2019.06F/vip/svt/pcie_test_suite_svt/P-2019.06-1/design_dir/src/sverilog/vcs/pciesvc_endec.sv(712) @ 124199.840 ns: 
    uvm_test_top.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail: ACTIVE_PL_LANE_ENDEC:8B10B_DECODING:endec_illegal_decode_4] 
    Decoder: Illegal decode received! (disparity error or code violation) 
    Incoming was 0x0, rd=0, rd'=0
  • UVM_WARNING pciesvc_ltssm.svp(1589) @ 124516.932 ns: 
    uvm_test_top.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail:ACTIVE_PL:LTSSM_OS_COUNT_RULES:phy_recovery_speed_electrical_idle_with_no_eios] 
    LTSSM: Electrical idle detected on lane 0 in state RECOVERY_SPEED without preceding EIOS.
  • UVM_ERROR /p/psg/EIP/synopsys/vip/vg_P-2019.06F/vip/svt/pcie_test_suite_svt/P-2019.06-1/design_dir/src/sverilog/vcs/pciesvc_serdes.sv(242) @ 382510.547 ns: 
    uvm_test_top.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail:ACTIVE_PL_LANE_SERDES:PROTOCOL:serdes_new_min_seen_14]: New min half bit period seen
    (was 0.062500, now is 0.048750 ns) - SERDES unlocked.
    
  • UVM_ERROR /p/psg/EIP/synopsys/vip/vg_P-2019.06F/vip/svt/pcie_test_suite_svt/P-2019.06-1/design_dir/src/sverilog/vcs/pciesvc_serdes.sv(242) @ 519982.547 ns: 
    uvm_test_top.secondary_tests_1.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail:ACTIVE_PL_LANE_SERDES:PROTOCOL:serdes_new_min_seen_1] : New min half bit period seen 
    (was 0.062500, now is 0.048750 ns) - SERDES unlocked.
    
  • UVM_ERROR /p/psg/EIP/synopsys/vip/vg_P-2019.06F/vip/svt/pcie_test_suite_svt/P-2019.06-1/design_dir/src/sverilog/vcs/pciesvc_serdes.sv(242) @ 508334.547 ns: 
    uvm_test_top.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail:ACTIVE_PL_LANE_SERDES:PROTOCOL:serdes_new_min_seen_4] : New min half bit period seen 
    (was 0.062500, now is 0.048750 ns) - SERDES unlocked.
    
  • UVM_ERROR /p/psg/EIP/synopsys/vip/vg_P-2019.06F/vip/svt/pcie_test_suite_svt/P-2019.06-1/design_dir/src/sverilog/vcs/pciesvc_serdes.sv(242) @ 389018.547 ns: 
    uvm_test_top.secondary_tests_3.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail:ACTIVE_PL_LANE_SERDES:PROTOCOL:serdes_new_min_seen_3] : New min half bit period seen 
    (was 0.062500, now is 0.048750 ns) - SERDES unlocked.
    
  • UVM_ERROR /p/psg/EIP/synopsys/vip/vg_P-2019.06F/vip/svt/pcie_test_suite_svt/P-2019.06-1/design_dir/src/sverilog/vcs/pciesvc_serdes.sv(242) @ 510328.547 ns: 
    uvm_test_top.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail:ACTIVE_PL_LANE_SERDES:PROTOCOL:serdes_new_min_seen_3] : New min half bit period seen 
    (was 0.062500, now is 0.048750 ns) - SERDES unlocked.
    

Link equalization is bypassed in FASTSIM mode, Verification IP or Bus Functional Model is modified so that it does not expect equalization states during link training. The support from the verification IP vendor is required for the modified verification IP.

LTSSM state transition in FASTSIM mode (no EQ): RCVRY_SPEED -> RCVRY_LOCK -> RCVRY_RCVRCFG -> RCVRY_IDLE -> L0

LTSSM state transition without FASTSIM (skip EQ2 & EQ3): RCVRY_SPEED -> RCVRY_LOCK -> RCVRY_EQ0 -> RCVRY_EQ1 -> RCVRY_LOCK -> RCVRY_RCVRCFG -> RCVRY_IDLE -> L0

Note: FASTSIM mode support is a simple test case as defined in our design example simulation testbench.
Note: FASTSIM is not supported for Power Management Events and independent refclk simulation. In Intel® Quartus® Prime software 23.3 release, FASTSIM is supported for all simulators.