F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/11/2023
Public

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8.2.4.2.2. Event Counter

This tab allows you to read the error events like the number of receiver errors, framing errors, etc. for each port. You can use the Clear P0 counter/Clear P1 counter to reset the error counter.

Figure 79. Example of F-Tile Event Counter Tab
Note: P# Gen 2 speed change, Tx ack DLLP, Rx ack DLLP, Tx update flow control DLLP & Rx update flow control DLLP value would be corrupted when there is a reset such as SBR/Link Disable