GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683136
Date 9/13/2023
Document Table of Contents

Guideline: Swap datain_h and datain_l Ports in Migrated IP

When you migrate your GPIO IP from previous devices to the GPIO IP, you can turn on Use legacy top-level port names option in the GPIO IP parameter editor. However, the behavior of these ports in the GPIO IP is different than in the IP used for the Stratix® V, Arria® V, and Cyclone® V devices.

The GPIO IP drives these ports to the output registers on these clock edges:

  • datain_h—on the falling edge of outclock
  • datain_l—on the rising edge of outclock

If you migrated your GPIO IP from Stratix® V, Arria® V, and Cyclone® V devices, swap the datain_h and datain_l ports when you instantiate the IP generated by the GPIO IP.