SDI II Intel® FPGA IP User Guide

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ID 683133
Date 10/05/2023
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Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Quick Reference 2. SDI II IP Core Overview 3. SDI II IP Core Getting Started 4. SDI II IP Core Parameters 5. SDI II IP Core Functional Description 6. SDI II IP Core Signals 7. SDI II IP Core Design Considerations 8. SDI II IP Core Testbench and Design Examples 9. SDI II Intel® FPGA IP User Guide Archives 10. Document Revision History for the SDI II Intel® FPGA IP User Guide
2. SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. SDI II IP Core Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Design Walkthrough 3.3. SDI II IP Core Component Files 3.4. Compiling the SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Intel® Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion 5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion 5.4.3. SMPTE RP168 Switching Support 5.4.4. SD 20-Bit Interface for Dual/Triple Rate 5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices 5.4.6. Intel FPGA Video Streaming Interface
5.4.6. Intel FPGA Video Streaming Interface x
5.4.6.1. RGB Pixel Packing 5.4.6.2. YCbCr 444 Pixel Packing 5.4.6.3. YCbCr 422 Pixel Packing 5.4.6.4. Supported Modes
6. SDI II IP Core Signals x
6.1. SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Timing Violation 7.3. SDI II IP Core Registers
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices 7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices 7.1.3. Handling Transceiver in Intel Agilex® 7 F-Tile Devices
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices x
7.1.1.1. Modifying the Transceiver Reconfiguration Controller 7.1.1.2. Modifying the Reconfiguration Management 7.1.1.3. Modifying the Reconfiguration Router
7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices x
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core 7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel 7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates 7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel 7.1.2.5. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.7. Unused Transceiver Channels 7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices
7.1.3. Handling Transceiver in Intel Agilex® 7 F-Tile Devices x
7.1.3.1. System PLL Clocking Mode 7.1.3.2. RX Transceiver Settings 7.1.3.3. TX Transceiver Settings 7.1.3.4. Unused Transceiver Tiles 7.1.3.5. Dynamic Reconfiguration 7.1.3.6. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
7.1.3.2. RX Transceiver Settings x
7.1.3.2.1. Multi-rate Designs 7.1.3.2.2. Triple-rate Designs 7.1.3.2.3. Single-rate Designs
7.3. SDI II IP Core Registers x
7.3.1. SDI II Tx Register Summary 7.3.2. SDI II Tx Register Description 7.3.3. SDI II Rx Register Summary 7.3.4. SDI II Rx Register Description
8. SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile Devices 8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile Devices x
8.1.1. Design Example Presets
8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices x
8.2.1. Design Example Components 8.2.2. Design Reference 8.2.3. Simulating the SDI II IP Core Design
8.2.1. Design Example Components x
8.2.1.1. Video Pattern Generator 8.2.1.2. Transceiver Reconfiguration Controller 8.2.1.3. Reconfiguration Management 8.2.1.4. Reconfiguration Router 8.2.1.5. Avalon® Memory-Mapped Interface Translators
8.2.2. Design Reference x
8.2.2.1. Video Pattern Generator Signals 8.2.2.2. Transceiver Reconfiguration Controller Signals 8.2.2.3. Reconfiguration Management Parameters 8.2.2.4. Reconfiguration Router Signals
8.2.3. Simulating the SDI II IP Core Design x
8.2.3.1. Simulation Run Time
1. SDI II Intel® FPGA IP Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide

6.3. Receiver Protocol Signals

Table 20.  Receiver Protocol Signals—Synchronous to rx_coreclk
Signal Width Direction Description
rx_coreclk_is_ntsc_paln

1

Input

Indicates to the receiver core if rx_coreclk or rx_coreclk_hd is at NSTC (1/1.001) or PAL (1) rate. This signal is required for the receiver core to detect the incoming video rate as NTSC or PAL.

  • 0 = PAL rate (when rx_coreclk = 297 / 148.5 MHz or rx_coreclk_hd = 74.25 MHz)
  • 1 = NTSC rate (when rx_coreclk = 296.70 / 148.35 MHz or rx_coreclk_hd = 74.175 MHz)
Note: Not applicable for SD-SDI and protocol only configurations.
Note: Not applicable for Intel Agilex® 7 device family.
rx_std_in

3

Input

Indicates to the receiver core protocol block the video standard received by the transceiver block.

Note: Applicable for 3G-SDI, dual-rate, and triple-rate receiver protocol only configurations. Not applicable for Intel Agilex® 7 F-Tile, Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_clkout_is_ntsc_paln

1

Output

Indicates that the receiver core is receiving video rate at NSTC (1/1.001) or PAL (1).
  • 0 = PAL rate (rx_clkout = 148.5 MHz or 74.25 MHz)
  • 1 = NTSC rate (when rx_clkout = 148.35 MHz or 74.175 MHz)
Note: Not applicable for SD-SDI and protocol only modes.
rx_std (for transceiver only configurations)

3

Output

Receiver video standard .

  • 3'b000: SD-SDI
  • 3'b001: HD-SDI
  • 3'b011: 3G-SDI
Note: Applicable for 3G-SDI, dual-rate, and triple-rate configurations only. Not applicable for Intel Agilex® 7 F-Tile, Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
Table 21.  Receiver Protocol Signals—Synchronous to rx_clkout or xcvr_rxclk
Note: S = Indicates the number of 20-bit interfaces; 4 for multi-rate (up to 12G) mode and 1 for other modes.
Signal Width Direction Description
rx_datain

20S

Input

Receiver parallel data from the transceiver.

For Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices, this signal is directly connected to the rx_parallel_data signal from the transceiver.
Note: If you are not enabling the simplified data interface, refer to the Transceiver parameter editor or the Transceiver PHY IP Core User Guide for proper data bit mapping.

For older supported devices, this signal is directly connected to the rx_dataout signal from the SDI receiver in transceiver mode.

Note: Available only in protocol mode.
rx_datain_b

20

Input

Receiver parallel data from the transceiver for link B.

This signal is directly connected to the rx_dataout_b signal from the SDI receiver in transceiver mode.

Note: Applicable for HD-SDI dual link protocol only configuration. Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
rx_datain_valid

1

Input

Data valid from the oversampling logic. Assertion of this signal indicates the current data on rx_datain is valid. The timing (H: High, L: Low) for each video standard has the following settings:

  • SD-SDI = 1H 4L 1H 5L
  • HD-SDI = H
  • 3G-SDI = H
  • HD-SDI Dual Link = H
  • Dual rate = SD (1H 4L 1H 5L); HD (H)
  • Triple rate = SD (1H 4L 1H 5L); HD (H); 3G (H)
  • Multi rate (up to 12G) = SD (1H 4L 1H 5L); HD (H); 3G/6G/12G (H)

This signal is directly connected to the rx_dataout_valid signal from the SDI receiver in transceiver mode.

Note: Applicable for protocol only configuration. Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
rx_datain_valid_b

1

Input

Data valid from the oversampling logic. Assertion of this signal indicates the current data on rx_datain_b is valid.

This signal is directly connected to the rx_dataout_valid_b signal from the SDI receiver in transceiver mode.

Note: Applicable for HD-SDI dual link receiver protocol only configuration. Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
rx_trs_loose_lock_in

1

Input

Indicates that the receiver protocol block detects a single and valid TRS locking signal. This signal must be driven by rx_trs_loose_lock_out of the receiver protocol block.

Note: Applicable for receiver transceiver configuration only. Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
rx_trs_loose_lock_in_b

1

Input

Indicates that the receiver protocol block for link B detects a single and valid TRS locking signal. This signal must be driven by rx_trs_loose_lock_out_b of the receiver protocol block.

Note: Applicable for HD-SDI dual link receiver transceiver configuration only. Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
rx_trs_in 1 Input

The signal driven by rx_trs to indicate to the PHY management block that the receiver protocol block detected a valid TRS.

Note: Applicable for receiver transceiver configuration only. Not applicable for Intel Agilex® 7 F-Tile, Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_dataout

20S

Output

Receiver parallel data out.

In dual-rate or triple-rate mode:

  • Only lower 10 bits are valid for SD-SDI when SD Interface Bit Width = 10.
In multi-rate mode:
  • HD/3G-SDI: Only lower 20 bits are valid
  • 6G-SDI: Only lower 40 bits are valid

For bit ordering, refer to tx_datain signal description.

Note: Not applicable when Enable active video data protocols = AXIS-VVP Full.
rx_dataout_b

20

Output

Parallel data out signal for the receiver (link B).

Note: Applicable for HD-SDI dual link configuration only.
rx_dataout_valid

1

Output

Data valid from the oversampling logic. The receiver asserts this signal to indicate current data on rx_dataout is valid. The timing (H: High, L: Low) for each video standard has the following settings:

  • SD-SDI = 1H 4L 1H 5L
  • HD-SDI = H
  • 3G-SDI = H
  • HD-SDI Dual Link = H
  • Dual rate = SD (1H 4L 1H 5L); HD (H)
  • Triple rate = SD (1H 4L 1H 5L); HD (H); 3G (H)
  • Multi rate (up to 12G) = SD (1H 4L 1H 5L); HD (H); 3G/6G/12G (H)

The 1H4L 1H5L cadence for SD-SDI repeats indefinitely in an ideal case where the video source clock matches the CDR reference clock source. In a typical scenario, you may observe the cadence being shifted periodically (for instance, 1H4L 1H5L 1H5L 1H4L).

Note: Not applicable when Enable active video data protocols = AXIS-VVP Full.
rx_dataout_valid_b

1

Output

Data valid from the oversampling logic. The receiver asserts this signal to indicate current data on rx_dataout_b is valid. The timing (H: High, L: Low) for each video standard is identical to the rx_dataout_valid signal.
Note: Applicable for HD-SDI dual link configuration only.
rx_f

1S

Output

Field bit timing signal. This signal indicates which video field is currently active. For interlaced frame, 0 means first field (F0) while 1 means second field (F1). For progressive frame, the value is always 0.
Note: In Intel Agilex® 7 device family, this signal is not accurate enough to clock the external VCXO in SD-SDI mode for genlocking purpose. As a workaround, Intel recommends to use an external sync separator to generate this signal to the external VCXO. Alternatively, you can use parallel loopback without VCXO design example
rx_v

1S

Output

Vertical blanking interval timing signal. The receiver asserts this signal when the vertical blanking interval is active.

Note: In Intel Agilex® 7 device family, this signal is not accurate enough to clock the external VCXO in SD-SDI mode for genlocking purpose. As a workaround, Intel recommends to use an external sync separator to generate this signal to the external VCXO. Alternatively, you can use parallel loopback without VCXO design example
rx_h

1S

Output

Horizontal blanking interval timing signal. The receiver asserts this signal when the horizontal blanking interval is active.

Note: In Intel Agilex® 7 device family, this signal is not accurate enough to clock the external VCXO in SD-SDI mode for genlocking purpose. As a workaround, Intel recommends to use an external sync separator to generate this signal to the external VCXO. Alternatively, you can use parallel loopback without VCXO design example
rx_ap

1S

Output

Active picture interval timing signal. The receiver asserts this signal when the active picture interval is active.

Note: Not applicable when Enable active video data protocols = AXIS-VVP Full.
rx_std

3

Output

Receiver video standard with 10-bit multiplexed 10-bit parallel interface:

  • 3'b000: SD-SDI
  • 3'b001: HD-SDI
  • 3'b011: 3G-SDI Level A 10-bit Multiplex
  • 3'b010: 3G-SDI Level B 10-bit Multiplex
  • 3'b101: 6G-SDI 10-bit Multiplex Type 1
  • 3'b100: 6G-SDI 10-bit Multiplex Type 2
  • 3'b111: 12G-SDI 10-bit Multiplex Type 1
  • 3'b110: 12G-SDI 10-bit Multiplex Type 2
Note: For 6G and 12G-SDI, there are a few modes of data mapping for different image formats, and each of these modes requires different types of 10-bit Multiplex interface. For more details on the modes of data mapping and the type of 10-bit multiplexed interface, please refer to the SMPTE official documentation.

For instance, ST2081-10 Single link 6G-SDI has three modes of Data Mapping (Mode 1 – Mode 3).

Mode 2 and Mode 3 are assigned to 10-bit Multiplex Type 1.

While for Mode 1, it is assigned to 10-bit Multiplex Type 2.

This signal is only applicable for 3G-SDI, dual rate, triple rate, and multi rate.
rx_format

4S

Output

Indicates the format for the received video transport.

Refer to rx_format for more information about the video format values.
Note: For 3G-SDI and a higher data rate, ST425 Payload ID feature is mandatory. Intel recommends extracting the picture format information from the Payload ID’s byte data.
rx_eav

1S

Output

Receiver output that indicates current TRS is EAV. This signal is asserted at the fourth word of TRS, which is the XYZ word.

Note: Not applicable when Enable active video data protocols = AXIS-VVP Full.
rx_trs

1S

Output

Receiver output that indicates current word is TRS. This signal is asserted at the first word of 3FF 000 000 TRS.

Note: Not applicable when Enable active video data protocols = AXIS-VVP Full.
rx_ln

11S

Output

Receiver line number output.

Note: Applicable for all modes except SD-SDI.
Note: Not applicable when Enable active video data protocols = AXIS-VVP Full.
rx_ln_b

11S

Output

Receiver line number output for link B.
Note: Applicable for 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate (up to 12G) modes only.
Note: Not applicable when Enable active video data protocols = AXIS-VVP Full.
rx_align_locked

1

Output

Alignment locked, indicating that a TRS has been spotted and word alignment is performed.

rx_align_locked_b

1

Output

Alignment locked for link B, indicating that a TRS has been spotted and word alignment is performed.

Note: Applicable for HD-SDI dual link configuration only.
rx_trs_locked

1S

Output

TRS locked, indicating that six consecutive TRSs with same timing has been spotted.

rx_trs_locked_b

1

Output

TRS locked for link B, indicating that six consecutive TRSs with same timing has been spotted.

Note: Applicable for HD-SDI dual link configuration only.
rx_frame_locked

1

Output

Frame locked, indicating that multiple frames with same timing has been spotted.

rx_frame_locked_b

1

Output

Frame locked for link B, indicating that multiple frames with same timing has been spotted.

Note: Applicable for HD-SDI dual link configuration only.
rx_dl_locked

1

Output

Dual link locked, indicating that both ports are aligned.

Note: Applicable for HD-SDI dual link configuration only.
rx_trs_loose_lock_out

1

Output

Indicates that the receiver protocol block detects a single and valid TRS locking signal. This signal must be used to drive rx_trs_loose_lock_in of the receiver transceiver block.

Note: Applicable for protocol only configuration. Not applicable for Intel Agilex® 7 F-Tile, Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_trs_loose_lock_out_b

1

Output

Indicates that the receiver protocol block for link B detects a single and valid TRS locking signal. This signal must be used to drive rx_trs_loose_lock_in_b of the receiver transceiver block.

Note: Applicable for HD-SDI dual link protocol only configuration. Not applicable for Intel Agilex® 7 F-Tile, Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_crc_error_c

1S

Output

CRC error on chroma channel. Applicable only when you enable CRC checking.

Note: Applicable for all modes except SD-SDI.
rx_crc_error_y

1S

Output

CRC error on luma channel.

Note: Applicable only when you enable CRC checking. Applicable for all modes except SD-SDI.
rx_crc_error_c_b

1S

Output

CRC error on chroma channel for link B.

Note: Applicable only when you enable CRC checking. Applicable for 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate modes only.
rx_crc_error_y_b

1S

Output

CRC error on luma channel for link B. Applicable only when you enable CRC checking.

Note: Applicable for 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate modes only.
rx_vpid_byte1

8S

Output

The core extracts payload ID byte 1.

Applicable only when you enable the Extract Payload ID (SMPTE ST 352) option.

Note: For Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
rx_vpid_byte2

8S

Output

The core extracts payload ID byte 2.

Applicable only when you enable the Extract Payload ID (SMPTE ST 352) option.

Note: For Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
rx_vpid_byte3

8S

Output

The core extracts payload ID byte 3.

Applicable only when you enable the Extract Payload ID (SMPTE ST 352) option.

Note: For Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
rx_vpid_byte4

8S

Output

The core extracts payload ID byte 4.

Applicable only when you enable the Extract Payload ID (SMPTE ST 352) option.

Note: For Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
rx_vpid_valid

1S

Output

Indicates that the extracted payload ID is valid.

Applicable only when you enable the Extract Payload ID (SMPTE ST 352) option.

Note: For Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
rx_vpid_checksum_error

1S

Output

Indicates that the extracted payload ID has a checksum error.

Applicable only when you enable the Extract Payload ID (SMPTE ST 352) option.

rx_vpid_byte1_b

8S

Output

The core extracts payload ID byte 1 for link B.

Applicable only when you enable the Extract Payload ID (SMPTE ST 352) option.

Note: Applicable for 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate (up to 12G) modes only.
Note: For 3G-SDI, HD-SDI dual link, triple rate, multi rate (up to 12G) and Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
rx_vpid_byte2_b

8S

Output

The core extracts payload ID byte 2 for link B.

Applicable only when you enable the Extract Payload ID (SMPTE ST 352) option.

Note: Applicable for 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate (up to 12G) modes only.
Note: For 3G-SDI, HD-SDI dual link, triple rate, multi rate (up to 12G) and Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
rx_vpid_byte3_b

8S

Output

The core extracts payload ID byte 3 for link B.

Applicable only when you enable the Extract Payload ID (SMPTE ST 352) option.

Note: Applicable for 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate (up to 12G) modes only.
Note: For 3G-SDI, HD-SDI dual link, triple rate, multi rate (up to 12G) and Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
rx_vpid_byte4_b

8S

Output

The core extracts payload ID byte 4 for link B.

Applicable only when you enable the Extract Payload ID (SMPTE ST 352) option.

Note: Applicable for 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate (up to 12G) modes only.
Note: For 3G-SDI, HD-SDI dual link, triple rate, multi rate (up to 12G) and Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
rx_vpid_valid_b

1S

Output

Indicates that the extracted payload ID for link B is valid.

Applicable only when you enable the Extract Payload ID (SMPTE ST 352) option.

Note: Applicable for 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate (up to 12G) modes only.
Note: For 3G-SDI, HD-SDI dual link, triple rate, multi rate (up to 12G) and Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
rx_vpid_checksum_error_b

1S

Output

Indicates that the extracted payload ID for link B has a checksum error.

Applicable only when you enable the Extract Payload ID (SMPTE ST 352) option.

Note: Applicable for 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate (up to 12G) modes only.
Note: For 3G-SDI, HD-SDI dual link, triple rate, multi rate (up to 12G) and Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
rx_line_f0

11S

Output

Line number of field 0 (F0) of the payload ID location. Requires two complete frames to update this signal.

Applicable only when you enable the Extract Video Payload ID (SMPTE ST 352 ) option.

Note: For Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
rx_line_f1

11S

Output

Line number of field 1 (F1) of the payload ID location. Requires two complete frames to update this signal.

Applicable only when you enable the Extract Video Payload ID (SMPTE ST 352) option.

Note: For Receiver Options – Extract Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.

Section Content
rx_format

Level Two Title