AN 932: Flash Access Migration Guidelines from Control Block-Based Devices to SDM-Based Devices

ID 683127
Date 7/31/2023
Public

1.3. Using GPIO as Interface for Accessing Flash Devices

Figure 5. Accessing QSPI Flash

You can port over design in control block-based devices to SDM-based devices directly if the design is using the Generic Serial Flash Interface Intel® FPGA IP with exported flash pin to GPIO.

In some rare cases, the QSPI flash device is connected to GPIO pin in FPGA. The QSPI flash device is only used as a general purpose memory storage when it is connected to GPIO. The flash device can be accessed through the Generic Serial Flash Interface Intel® FPGA IP (recommended) or Generic QUAD SPI Controller II Intel® FPGA IP by selecting the option to export the SPI pin to GPIO.

In Intel® Stratix® 10 devices and Intel Agilex® FPGA portfolio, you can connect the flash devices to GPIO pin in the FPGA to use as general purpose memory storage as well. However, please take note that the parameter setting for the enable SPI pin interface must be enabled in the Generic Serial Flash Interface Intel® FPGA IP when you are using Intel® Stratix® 10 devices and Intel Agilex® FPGA portfolio to prevent error during compilation. This is because there is no dedicated Active Serial Memory Interface available in the Intel® Stratix® 10 devices and Intel Agilex® FPGA portfolio. For configuration purpose in these devices, you must connect the flash devices to the SDM I/O as described in the SDM-Based Devices section.