Intel® Quartus® Prime Pro Edition User Guide: Third-party Synthesis
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2.10.1.7. Other Synplify Software Attributes for Creating Black Boxes
Adding Timing Models to Black Boxes in Verilog HDL
module ram32x4(z,d,addr,we,clk); /* synthesis syn_black_box syn_tcol="clk->z[3:0]=4.0" syn_tpd1="addr[3:0]->[3:0]=8.0" syn_tsu1="addr[3:0]->clk=2.0" syn_tsu2="we->clk=3.0" */ output [3:0]z; input[3:0]d; input[3:0]addr; input we input clk endmodule
The following additional attributes are supported by the Synplify software to communicate details about the characteristics of the black box module within the HDL code:
- syn_resources—Specifies the resources used in a particular black box.
- black_box_pad_pin—Prevents mapping to I/O cells.
- black_box_tri_pin—Indicates a tri-stated signal.
For more information about applying these attributes, refer to the Synopsys FPGA Synthesis Reference Manual.