Intel® Quartus® Prime Pro Edition User Guide: Third-party Synthesis

ID 683122
Date 12/12/2023
Public
Document Table of Contents

1.8.6.5. Controlling DSP Block Inference

By default, the Precision RTL software infers the ALTMULT_ADD or ALTMULT_ACCUM IP cores appropriately in your design. These IP cores allow the Intel® Quartus® Prime software to select either logic or DSP blocks, depending on the device utilization and the size of the function.

You can use the extract_mac attribute to prevent inference of an ALTMULT_ADD or ALTMULT_ACCUM IP cores in a certain module or entity.

Table 4.  Options for extract_mac Attribute Controlling DSP Implementation
Value Description
TRUE The ALTMULT_ADD or ALTMULT_ACCUM IP core is inferred.
FALSE The ALTMULT_ADD or ALTMULT_ACCUM IP core is not inferred.

To control inference, use the extract_mac attribute with the appropriate value from the examples below in your HDL code.

Setting the extract_mac Attribute in Verilog HDL

//synthesis attribute <module name> extract_mac <value>

Setting the extract_mac Attribute in VHDL

ATTRIBUTE extract_mac: BOOLEAN;
ATTRIBUTE extract_mac OF <entity name>: ENTITY IS <value>;

Using extract_mac, dedicated_mult, and preserve_signal in Verilog HDL

To control the implementation of the multiplier portion of a multiply-accumulator or multiply-adder, you must use the dedicated_mult attribute.

You can use the extract_mac, dedicated_mult, and preserve_signal attributes (in Verilog HDL and VHDL) to implement the given DSP function in logic in the Intel® Quartus® Prime software.

module unsig_altmult_accuml (dataout, dataa, datab, clk, aclr, clken);
   input [7:0} dataa, datab;
   input clk, aclr, clken;
   output [31:0] dataout;

   reg    [31:0] dataout;
   wire   [15:0] multa;
   wire   [31:0] adder_out;

   assign multa = dataa * datab;

   //synthesis attribute multa preserve_signal TRUE
   //synthesis attribute multa dedicated_mult OFF
   assign adder_out = multa + dataout;

   always @ (posedge clk or posedge aclr)
   begin
      if (aclr)
      dataout <= 0;
      else if (clken)
      dataout <= adder_out;
   end

   //synthesis attribute unsig_altmult_accuml extract_mac FALSE
endmodule

Using extract_mac, dedicated_mult, and preserve_signal in VHDL

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
ENTITY signedmult_add IS
   PORT(
      a, b, c, d: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
      result: OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
   ATTRIBUTE preserve_signal: BOOLEANS;
   ATTRIBUTE dedicated_mult: STRING;
   ATTRIBUTE extract_mac: BOOLEAN;
   ATTRIBUTE extract_mac OF signedmult_add: ENTITY IS FALSE;
END signedmult_add;
ARCHITECTURE rtl OF signedmult_add IS
   SIGNAL a_int, b_int, c_int, d_int : signed (7 DOWNTO 0);
   SIGNAL pdt_int, pdt2_int : signed (15 DOWNTO 0);
   SIGNAL result_int: signed (15 DOWNTO 0);
   ATTRIBUTE preserve_signal OF pdt_int: SIGNAL IS TRUE;
   ATTRIBUTE dedicated_mult OF pdt_int: SIGNAL IS "OFF";
   ATTRIBUTE preserve_signal OF pdt2_int: SIGNAL IS TRUE;
   ATTRIBUTE dedicated_mult OF pdt2_int: SIGNAL IS "OFF";
BEGIN
   a_int <= signed (a);
   b_int <= signed (b);
   c_int <= signed (c);
   d_int <= signed (d);
   pdt_int <= a_int * b_int;
   pdt2_int <= c_int * d_int;
   result_int <= pdt_int + pdt2_int;
   result <= STD_LOGIC_VECTOR(result_int);
END rtl;