1.1. Reed-Solomon II versus High-Speed Reed Solomon Intel® FPGA IP
1.2. High-speed Reed-Solomon IP Core Features
1.3. High-Speed Reed-Solomon IP Device Family Support
1.4. DSP IP Core Verification
1.5. High-speed Reed-Solomon IP Core Release Information
1.6. High-speed Reed-Solomon IP Core Performance and Resource Utilization
2.1.2. High-speed Reed-Solomon IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If a design has more than one IP core, the time-out behavior of the other IP cores may mask the time-out behavior of a specific IP core .
All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If there is more than one IP core in a design, a specific IP core's time-out behavior may be masked by the time-out behavior of the other IP cores. For IP cores, the untethered time-out is 1 hour; the tethered time-out value is indefinite. Your design stops working after the hardware evaluation time expires. The Quartus Prime software uses Intel® FPGA IP Evaluation Mode Files (.ocp) in your project directory to identify your use of the Intel® FPGA IP Evaluation Mode evaluation program. After you activate the feature, do not delete these files..
When the evaluation time expires, out_data goes low .
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