High-speed Reed-Solomon IP Core User Guide

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ID 683120
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the High-speed Reed-Solomon IP Core 2. High-speed Reed-Solomon IP Core Getting Started 3. High-speed Reed-Solomon IP Core Functional Description 4. High-speed Reed-Solomon IP Core User Guide Document Revision History A. High-Speed Reed-Solomon IP Core Document Archive
1. About the High-speed Reed-Solomon IP Core x
1.1. Reed-Solomon II versus High-Speed Reed Solomon Intel® FPGA IP 1.2. High-speed Reed-Solomon IP Core Features 1.3. High-Speed Reed-Solomon IP Device Family Support 1.4. DSP IP Core Verification 1.5. High-speed Reed-Solomon IP Core Release Information 1.6. High-speed Reed-Solomon IP Core Performance and Resource Utilization
2. High-speed Reed-Solomon IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. High-speed Reed-Solomon IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. High-speed Reed-Solomon IP Core Functional Description x
3.1. High-Speed Reed-Solomon Architecture 3.2. High-Speed Reed-Solomon IP Core Parameters 3.3. High-speed Reed-Solomon IP Core Interfaces and Signals
3.1. High-Speed Reed-Solomon Architecture x
3.1.1. High-Speed Reed-Solomon Encoder 3.1.2. High-Speed Reed-Solomon Decoder
3.3. High-speed Reed-Solomon IP Core Interfaces and Signals x
3.3.1. High-speed Reed-Solomon IP Core Signals
1. About the High-speed Reed-Solomon IP Core
2. High-speed Reed-Solomon IP Core Getting Started
3. High-speed Reed-Solomon IP Core Functional Description
4. High-speed Reed-Solomon IP Core User Guide Document Revision History
A. High-Speed Reed-Solomon IP Core Document Archive

3.1.2. High-Speed Reed-Solomon Decoder

When the decoder receives the encoded codeword, it uses the check symbols to detect errors and correct them. The decoder is a streaming decoder that allows continuous input data with no backpressure on the upstream component.
Figure 8. Codeword Decoding

The received encoded codeword may differ from the original codeword due to the noise in the channel. The decoder detects errors using several polynomials to locate the error location and the error value. When the decoder obtains the error location and value, the decoder corrects the errors in a codeword, and sends the codeword to the output. As the number of errors increases, the decoder gets to a stage where it can no longer correct but only detect errors, at which point the decoder asserts the out_error signal.

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