Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Stratix® 10 Devices
ID
683100
Date
8/05/2024
Public
1. Low Latency 100G Ethernet Intel FPGA IP Overview
2. Getting Started
3. IP Core Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Registers
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives
11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide
4.3.1. Low Latency 100G Ethernet Intel FPGA IP Core Preamble Processing
4.3.2. IP Core Strict SFD Checking
4.3.3. Low Latency 100G Ethernet Intel FPGA IP Core FCS (CRC-32) Removal
4.3.4. Low Latency 100G Ethernet Intel FPGA IP Core CRC Checking
4.3.5. Low Latency 100G Ethernet Intel FPGA IP Core Malformed Packet Handling
4.3.6. RX CRC Forwarding
4.3.7. Inter-Packet Gap
4.3.8. RX PCS
4.3.9. RX RSFEC
7.8.1. AN/LT Sequencer Config
7.8.2. AN/LT Sequencer Status
7.8.3. Auto Negotiation Config Register 1
7.8.4. Auto Negotiation Config Register 2
7.8.5. Auto Negotiation Status Register
7.8.6. Auto Negotiation Config Register 3
7.8.7. Auto Negotiation Config Register 4
7.8.8. Auto Negotiation Config Register 5
7.8.9. Auto Negotiation Config Register 6
7.8.10. Auto Negotiation Status Register 1
7.8.11. Auto Negotiation Status Register 2
7.8.12. Auto Negotiation Status Register 3
7.8.13. Auto Negotiation Status Register 4
7.8.14. Auto Negotiation Status Register 5
7.8.15. Link Training Config Register 1
7.8.16. Link Training Config Register 2
7.8.17. Link Training Status Register 1
7.8.18. Link Training Config Register for Lane 0
7.8.19. Link Training Frame Contents for Lane 0
7.8.20. Local Transceiver TX EQ 1 Settings for Lane 0
7.8.21. Local Transceiver TX EQ 2 Settings for Lane 0
7.8.22. Local Link Training Parameters
7.8.23. Link Training Config Register for Lane 1
7.8.24. Link Training Frame Contents for Lane 1
7.8.25. Local Transceiver TX EQ 1 Settings for Lane 1
7.8.26. Local Transceiver TX EQ 2 Settings for Lane 1
7.8.27. Link Training Config Register for Lane 2
7.8.28. Link Training Frame Contents for Lane 2
7.8.29. Local Transceiver TX EQ 1 Settings for Lane 2
7.8.30. Local Transceiver TX EQ 2 Settings for Lane 2
7.8.31. Link Training Config Register for Lane 3
7.8.32. Link Training Frame Contents for Lane 3
7.8.33. Local Transceiver TX EQ 1 Settings for Lane 3
7.8.34. Local Transceiver TX EQ 2 Settings for Lane 3
6.9. Flow Control Interface
Flow Control Interface signals become available when you turn on Enable MAC Flow Control in the parameter editor.
Signal Name |
Direction |
Description |
---|---|---|
pause_insert_tx0[(FCQN-1):0] pause_insert_tx1[(FCQN-1):0] |
Input | This signal is available if you specify pause on PFC.
The signal indicates to the MAC whether XON or XOFF Pause or PFC flow control frame should be sent.
1-bit mode request model: The IP core ignores pause_insert_tx1[(FCQN-1):0].
The following encoding is defined:
2-bit mode request model: The higher-order bit is in pause_insert_tx1[(FCQN-1):0] and the lower-order bit is in pause_insert_tx0[(FCQN-1):0]. The XON/XOFF request is a level-based request. The following encoding is defined:
|
pause_receive_rx[(FCQN-1):0] | Output | Each pause_receive_rx[(FCQN-1):0] bit indicates the corresponding queue is being paused. This is a level-based signal. |