Nios® V Processor Intel® FPGA IP Release Notes

ID 683098
Date 12/11/2023
Document Table of Contents

3.1. Nios® V/m Processor Intel® FPGA IP v2.0.0

Table 10.  v2.0.0 2023.12.11
Intel® Quartus® Prime Version Description Impact
  • Removed Atomic extension.
  • Updated the Nios® V/m Processor Internal Timer interface.
  • Renamed the IP display name from Nios® V/m Processor Intel® FPGA IP to Nios® V/m Microcontroller Intel® FPGA IP .
  • Added ECC module and non-pipelined configuration.
  • Changed Instruction and Data Manager Interfaces from AXI4 to AXI4-Lite.
  • Enhanced prefetch logic. Updated the following performance and benchmark numbers:
    • FMAX
    • Area
    • Dhrystone
    • CoreMark
  • Remove exceptionOffset and exceptionAgent parameters from _hw.tcl.
    Note: Only impacted BSP generation. No impact on RTL or circuit.
  • Changed debug reset:
    • Added ndm_reset_in port
    • Renamed dbg_reset to dbg_reset_out.
  • Migrated the example designs to the Intel® FPGA Design Store.
  • Enabled Zephyr RTOS.