1.8. F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP v7.0.0
Quartus® Prime Version | Description | Impact |
---|---|---|
22.3 | Added BO SCTH (Simulation, Compile, Timing, and Hardware) support.
Note: B0 FHT multi-lane designs support bonding by default, and non-bonded multi-lane designs are not supported.
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B0 Ordering Part Number (OPN) now provide hardware support and also run Simulations, Compilations, and Timing Analysis (SCT). |
IP migration to full rate Phase-Locked Loop (PLL) for both FHT and FGT transceivers. | Force upgrade to current release. | |
Removed lt_cfg2 bits from register map: 0x344[7:0](restart_link_training_ln7:0). | lt_cfg2 bits are no longer accessible. |