F-Tile Serial Lite IV Intel® FPGA IP User Guide

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ID 683074
Date 8/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide 2. F-Tile Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals 7. Control and Status Registers 8. Designing with F-Tile Serial Lite IV Intel® FPGA IP 9. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Altera FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation 4.6. 32-bit Soft CWBIN Counters 4.7. i_stats_snapshot Port 4.8. Deterministic Latency
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
4.8. Deterministic Latency x
4.8.1. Deterministic Latency Top Wrapper
4.8.1. Deterministic Latency Top Wrapper x
4.8.1.1. TX DL Shim Wrapper 4.8.1.2. RX DL Shim Wrapper 4.8.1.3. Deterministic Latency Design Considerations
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Control and Status Registers x
7.1. F-Tile Serial Lite IV Intel® FPGA IP Soft CSR
8. Designing with F-Tile Serial Lite IV Intel® FPGA IP x
8.1. Reset Guidelines 8.2. Error Handling Guidelines 8.3. Analog Parameter Settings
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals
7. Control and Status Registers
8. Designing with F-Tile Serial Lite IV Intel® FPGA IP
9. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide

4.8.1.3. Deterministic Latency Design Considerations

The TX/RX core clock should be faster than the TX/RX user clock to overcome the inefficiency due to CW insertion and tx_ready de-assertion due to FEC_AM insertion and tx_ready deassertion events for BASIC mode.

For safety, a 10% margin between the user clock and core clock needs to be maintained to avoid any loss of data.

In summary, the following are the requirements that you must follow when the DL feature is enabled, which will have a deterministic latency value between user the TX data path and the user RX datapath:
  • F-Tile Serial Lite IV Intel® FPGA IP core clock should be ≥1.1 usrclk (user clock).
  • User clock for both TX and RX logic should be sourced from the same clock.
  • TX/RX DL shim wrapper user reset should be triggered whenever the F-Tile Serial Lite IV Intel® FPGA IP TX/RX core reset is triggered.
  • SYSREF_PERIOD parameter value of the SYSREF Pulse Generator is recommended to be set ≥1024 user clock cycles.
  • RBD value set should be greater than the latency of TX+RX (including TX DL shim and RX DL shim) in user_clk cycle + 13. There will be a maximum value before the DCFIFO within the RX DL module hits full. The default DCFIFO size of 128 is used in the Deterministic Latency Top Wrapper.

  • Calibrate the RBD value per IP variant used to ensure that the RX DL DCFIFO will not hit the empty/full scenario, else the IP latency will no longer be deterministic and valid.

    For the generated SL4 example design, the recommended DL RBD requirement as shown (in user clock cycles):
    • 184 < RBD < 282
    Note: The RBD maximum value can be further increased by increasing the RX DL wrapper DCFIFO size manually.
Table 24.  Recommended Deterministic Latency RBD values
CRC Soft CWBIN Counters Latency (in TX user clock cycle) Recommended Minimum RBD Delay Value (avoid RX DCFIFO empty) Recommended Maximum RBD Delay Value (avoid RX DCFIFO full)
On On 172 185

279

274 (system PLL frequency > transceiver clock frequency)
Off On 162 175

269

264 (system PLL frequency > transceiver clock frequency)
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