F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 9/26/2022
Public

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4.3. F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture

The F-Tile Serial Lite IV Intel® FPGA IP has four clock inputs which generate clocks to different blocks:
  • Transceiver reference clock (xcvr_ref_clk)—Input clock from external clock chips or oscillators which generates clocks for TX MAC, RX MAC, and TX and RX custom PCS blocks. Refer to Parameters for supported frequency range.
  • TX core clock (tx_core_clk)—This clock is derived from transceiver PLL is used for TX MAC. This clock is also an output clock from the F-tile transceiver to connect to the TX user logic.
  • RX core clock (rx_core_clk)—This clock is derived from the transceiver PLL is used for RX deskew FIFO and RX MAC. This clock is also an output clock from the F-tile transceiver to connect to the RX user logic.
  • Clock for transceiver reconfiguration interface (reconfig_clk)—input clock from external clock circuits or oscillators which generates clocks for F-tile transceiver reconfiguration interface in both TX and RX datapaths. The clock frequency is 100 to 162 MHz.

The following block diagram shows F-Tile Serial Lite IV Intel® FPGA IP clock domains and the connections within the IP.

Figure 22.  F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture