1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide 2. F-Tile Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with F-Tile Serial Lite IV Intel® FPGA IP 8. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives 9. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
|Intel® Quartus® Prime Design Suite 22.3|
|IP Version 7.0.0|
This document describes IP features, architecture description, steps to generate, and guidelines to design the F-Tile Serial Lite IV Intel® FPGA IP using the F-tile transceivers in Intel® Agilex™ devices.
This document is intended for the following users:
- Design architects to make IP selection during the system-level design planning phase
- Hardware designers when integrating the IP into their system-level design
- Validation engineers during the system-level simulation and hardware validation phases
The following table lists other reference documents that are related to the F-Tile Serial Lite IV Intel® FPGA IP.
|F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide||This document provides generation, usage guidelines, and functional description of the F-Tile Serial Lite IV Intel® FPGA IP design examples in Intel® Agilex™ devices.|
|Intel® Agilex™ Device Data Sheet||
This document describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Agilex™ devices.
Acronyms and Glossary
|RS-FEC||Reed-Solomon Forward Error Correction|
|PMA||Physical Medium Attachment|
|PAM4||Pulse-Amplitude Modulation 4-Level|
|PCS||Physical Coding Sublayer|
|MII||Media Independent Interface|
|XGMII||10 Gigabit Media Independent Interface|
Did you find the information on this page useful?