F-Tile Interlaken Intel® FPGA IP Design Example User Guide

ID 683069
Date 10/04/2021
Public

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4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.10.04 21.3 3.0.0
  • Added support for new lane rate combinations. For more information, refer to Table: IP Supported Combinations of Number of Lanes and Data Rate.
  • Updated the supported simulator list in section: Hardware and Software Requirements.
  • Added new reset registers in section: Register Map.
2021.06.21 21.2 2.0.0 Initial release.