Designing for Stratix 10 Devices with Power in Mind

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ID 683058
Date 6/14/2016
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1.2. Power Estimation with Resource Utilization

The following estimates are based on hypothetical designs (referenced from previous generation devices) for Stratix® 10 devices. Both static and dynamic power consumption values are derived using Intel’s PowerPlay® Early Power Estimator.
  • Device—SG280 with F43 package
  • Device type—X
  • Junction Temperature—100°C
Table 1.  Power Estimation for Core Logic/FPGA Fabric
Resource Configuration Static Power 1 Dynamic Power
Low utilization ~ 50%

800K half-ALMs

High utilization ~ 90%

1.7M half-ALMs

Low speed configuration:
  • 500 MHz (Max. CLK)
  • 312 MHz (Avg. weighted CLK)
 NA 18 W 40 W
High speed configuration:
  • 750 MHz (Max. CLK)
  • 468 MHz (Avg. weighted CLK)
 NA 27 W 56 W
Table 2.  Power Estimation for M20K—20Kb Internal Memory Blocks
Resource Configuration Static Power Dynamic Power
Low utilization ~ 40%

4600 memory blocks

 High utilization ~ 70%

8500 memory blocks
Low speed configuration:
  • Single port
  • 500 MHz, 40% toggle
  • 70% R/W, 70% enable
  • 5 bits wide, 4096 bits deep
 2 W 3.7 W 7 W
High speed configuration:
  • True dual port
  • 800 MHz, 40% toggle
  • 70% R/W, 70% enable
  • 20 bits wide, 1024 bits deep
 2 W 16.5 W 30 W
Table 3.  Power Estimation for DSP Block
Resource Configuration Static Power Dynamic Power
Low utilization ~ 40%

2300 DSP blocks

 High utilization ~ 70%

4000 DSP blocks
Low speed configuration:
  • 500 MHz, 15% toggle
  • 3 registered stages
  • Without pre-adder
  • With coefficient
 2.5/4 W 5 W 8.6 W
High speed configuration:
  • 800 MHz, 15% toggle
  • 0 registered stages
  • With pre-adder
  • Without coefficient
 2.5/4 W 40 W 66 W
Table 4.  Power Estimation for Transceivers
Resource Configuration Static Power Dynamic Power
Low utilization

16 channels

 High utilization

96 channels
Low speed configuration:
  • 16 channels
  • 16 channels (PCIe Gen3)
  • 40 channels of 10G Ethernet with 1588
  • 24 channels @ 17.4 Gbps
2 W 5 W 40 W
High speed configuration:
  • 16 channels (PCIe Gen3)
  • 80 channels @ 17.4 Gbps
2 W 7 W 45 W
Table 5.  Power Estimation for Clocks
Resource Configuration Static Power Dynamic Power
Low utilization ~ 50% High utilization ~ 90%
Low speed configuration:
  • 254 MHz Avg. weighted CLK
  • 75% global + local enabled (with some CLK gating)
1 W 3 W 6 W
High speed configuration:
  • 364 MHz Avg. weighted CLK
  • 100% global + local enabled (without CLK gating)
1 W 7 W 13.5 W

Stratix® 10 devices are significantly bigger and faster in terms of density and performance than previous generations of FPGA devices. Correspondingly, there is a increase in power consumption even with the increase in power efficiency. Therefore, you should leverage the power reduction capabilities discussed in this application note and ensure that you plan for the thermal implications of the power consumption in your Stratix® 10 FPGA designs. For more information on thermal solutions for the Stratix® 10 device designs, consult your Intel support team.

Related Information
1 Independent of logic usage.
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