Designing for Stratix 10 Devices with Power in Mind

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ID 683058
Date 6/14/2016
Public
Document Table of Contents
Document Table of Contents x
1. Designing for Stratix 10 Devices with Power in Mind A. Document Revision History
1. Designing for Stratix 10 Devices with Power in Mind x
1.1. Power Optimization Techniques and Recommendations 1.2. Power Estimation with Resource Utilization
1. Designing for Stratix 10 Devices with Power in Mind
A. Document Revision History

1. Designing for Stratix 10 Devices with Power in Mind

Stratix® 10 devices offer advanced features and capabilities for power reduction such as SmartVID, power gating of unused blocks, low-power transceivers, low-voltage devices, and low-static power devices.

Additionally, Stratix® 10 devices are the only high-performance FPGAs and programmable SoCs developed on Intel’s industry-leading 14 nm Tri-Gate processes, offering up to 70% lower power compared to the previous generation.

This application note highlights the power optimizing strategies that you can implement while you design using the Stratix® 10 FPGAs. It also showcases the power consumption statistics for resources utilized in various design scenarios.

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